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? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor technical data the mpc8347e contains a powe rpc? processor core with system logic required for networking, storage, and general-purpose embedded appl ications. for functional characteristics of the processor, refer to the mpc8349e powerquicc ii? pro integrated host processor reference manual, rev. 1 . to locate any published errata or updates for this document, contact your freescale sales office. mpc8347eec rev. 5, 10/2005 contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11 5. ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. duart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. ethernet: three-speed ethernet, mii management . 22 8. usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11. i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12. pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14. gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 17. package and pin listings . . . . . . . . . . . . . . . . . . . . . 60 18. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 19. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 20. system design information . . . . . . . . . . . . . . . . . . 101 21. electrical characteristics . . . . . . . . . . . . . . . . . . . . 106 22. document revision history . . . . . . . . . . . . . . . . . . 110 23. ordering information . . . . . . . . . . . . . . . . . . . . . . . 110 mpc8347e powerquicc? ii pro integrated host processor hardware specifications
mpc8347e powerquicc? ii pro integrated host processor hardware specifications, rev. 5 2 freescale semiconductor overview 1 overview this section provides a high-level overview of the mpc8347e features. figure 1 shows the major functional units within the mpc8347e. figure 1. mpc8347e block diagram major features of the mpc8347e are as follows: ? embedded powerpc processor core; operates at up to 667 mhz ? high-performance, superscalar processor core ? floating-point, integer, lo ad/store, system register, and branch processing units ? 32-kbyte instruction cach e, 32-kbyte data cache ? lockable portion of l1 cache ? dynamic power management ? software-compatible with the other freescale proce ssor families that implement the powerpc architecture ? ddr sdram memory controller ? programmable timing s upporting ddr-1 sdram ? 32-or 64-bit data interface, up to 333 mhz data rate ? four banks of memory, each up to 1 gbyte ? dram chip configurations from 64 mb it to 1 gbit with x8/x16 data ports ? full ecc support ? page mode support (up to 16 simultaneous open pages) ? contiguous or discontiguous memory mapping ? read-modify-write support ? sleep mode support fo r self refresh sdram ? supports auto refreshing duart dual i 2 c timers gpio security interrupt controller dual role high-speed local bus ddr sdram controller host 32kb d-cache e300 core 32kb i-cache usb 2.0 10/100/1000 seq pci dma ethernet 10/100/1000 ethernet
mpc8347e powerquicc? ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 3 overview ? on-the-fly power management using cke ? registered dimm support ? 2.5-v sstl2 compatible i/o ? dual three-speed (10/100/1000) et hernet controllers (tsecs) ? dual ieee 802.3, 802.3u, 820.3x, 802.3z, 802.3 ac compliant controllers ? support for different ethe rnet physical interfaces: ? 1000 mbps ieee 802.3 gmii/rgmii , 802.3z tbi/rtbi, full-duplex ? 10/100 mbps ieee 802.3 mii full- and half-duplex ? buffer descriptors are backwards comp atible with mpc8260 and mpc860t 10/100 programming models ? 9.6-kbyte jumbo frame support ? rmon statistics support ? internal 2-kbyte transmit and 2-k byte receive fifo?s per tsec module ? mii management interface for control and status ? programmable crc ge neration and checking ?pci interface ? pci specification revision 2.2 compatible ? data bus width: ? 32-bit data pci interface that operates at up to 66 mhz, or ? pci 3.3-v compatible ? pci host bridge capabilities ? pci agent mode supported on pci interface ? support for pci to memory and memory to pci streaming ? memory prefetching of pci read accesses and support for delayed read transactions ? support for posting of processor to pci and pci to memory writes ? on-chip arbitration, s upporting 5 masters on pci ? support for accesses to all pci address spaces ? parity supported ? selectable hardware-enforced coherency ? address translation units for addres s mapping between hos t and peripheral ? dual address cycle support when target ? internal configuration regi sters accessible from pci ? security engine is optimized to handle all the algorithms associated with ipsec, ssl/tls, srtp, 802.11i, iscsi, and ike processing. the security engine contains f our crypto-channels, a controller, and a set of crypto executi on units (eus). the execution units are: ? public key execution unit (pkeu) supporting the following: ? rsa and diffie-hellman ? programmable field size up to 2048-bits
mpc8347e powerquicc? ii pro integrated host processor hardware specifications, rev. 5 4 freescale semiconductor overview ? elliptic curve cryptography ? f2m and f(p) modes ? programmable field size up to 511 bits ? data encryption standa rd execution unit (deu) ? des, 3des ? two key (k1, k2) or three key (k1, k2, k3) ? ecb and cbc modes for both des and 3des ? advanced encryption standard unit (aesu) ? implements the rinjdael symmetric key cipher ? key lengths of 128, 192, and 256 bits.two key ? ecb, cbc, ccm, and counter modes ? arc four execution unit (afeu) ? implements a stream cipher comp atible with the rc4 algorithm ? 40- to 128-bit programmable key ? message digest execution unit (mdeu) ? sha with 160- or 256-bit message digest ? md5 with 128-bit message digest ? hmac with either algorithm ? random number generator (rng) ? four crypto-channels, each supporting multi-command descriptor chains ? static and/or dynamic assignment of crypto- execution units via an integrated controller ? buffer size of 256 bytes for each execution uni t, with flow control for large data sizes ? universal serial bus (usb) dual role controller ? supports usb on-the-go mode, which incl udes both device and host functionality ? complies with usb specification rev. 2.0 ? supports operation as a stand-alone usb device ? supports one upstr eam facing port ? supports six programmable usb endpoints ? supports operation as a stand-alone usb host controller ? supports usb root hub with one downstream-facing port ? enhanced host controller in terface (ehci) compatible ? supports high-speed (480 mbps), full-speed ( 12 mbps), and low-speed (1.5 mbps) operations ? supports external phy with utmi, serial and utmi+ low-pin interface (ulpi) ? universal serial bus (usb ) multi-port host controller ? supports operation as a stand-alone usb host controller ? supports usb root hub with one or two downstream-facing ports
mpc8347e powerquicc? ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 5 overview ? enhanced host controller in terface (ehci) compatible (open host controller interface (ohci) in question) ? complies with usb specification rev. 2.0 ? supports high-speed (480 mbps), full-speed ( 12 mbps), and low-speed (1.5 mbps) operations ? supports a direct connection to a high- speed device without an external hub ? supports external phy with serial and low-pin count (ulpi) interfaces ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 133 mhz ? four chip selects support four external slaves ? up to eight-beat burst transfers ? 32-, 16-, and 8-bit port si zes are controlled by an on-chip memory controller ? three protocol engines availabl e on a per chip select basis: ? general-purpose chip select machine (gpcm) ? three user programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with conf igurable bus width (8-, 16-, or 32-bit) ? programmable interrupt controller (pic) ? functional and programming compatibility with the mpc8260 inte rrupt controller ? support for 8 external and 35 inte rnal discrete interrupt sources ? support for 1 external (optional) and 7 in ternal machine checkstop interrupt sources ? programmable highest priority request ? four groups of interrupts with programmable priority ? external and internal interrupt s directed to host processor ? redirects interrupts to external inta pin when in core disable mode. ? unique vector number fo r each interrupt source ? dual industry-standard i 2 c interfaces ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? system initialization data is optionally loaded from i 2 c-1 eprom by boot sequencer embedded hardware ? dma controller ? four independent virtual channels ? concurrent execution across multiple channels with pr ogrammable bandwidth control ? all channels accessible by local core and remote pci masters ? misaligned transfer capability
mpc8347e powerquicc? ii pro integrated host processor hardware specifications, rev. 5 6 freescale semiconductor overview ? data chaining and direct mode ? interrupt on completed segment and chain ? duart ? two 4-wire interfaces (rxd, txd, rts, cts) ? programming model compat ible with the origin al 16450 uart and the pc16550d ? serial peripheral interface (spi) ? master or slave support ? general-purpose parallel i/o (gpio) ? 52 parallel i/o pins multip lexed on various chip interfaces ? system timers ? periodic interrupt timer ? real-time clock ? software watchdog timer ? eight general-purpose timers ? ieee 1149.1 compliant, jtag boundary scan ? integrated pci bus and sdram clock generation
mpc8347e powerquicc? ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 7 overview
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 8 freescale semiconductor power characteristics 2 power characteristics the estimated typical power diss ipation for this family of mpc8347e devices is shown in table 1 . table 1. mpc8347e power dissipation 1 1 the values do not include i/o supply power (ovd d, lvdd, gvdd) or avdd. for io power values, see ta bl e 2 . core frequency (mhz) csb frequency (mhz) typical at t j = 65 typical 2 , 3 2 typical power is based on a voltage of vdd = 1.2 v, a junction temperature of t j = 105 c, and a dhrystone benchmark application. 3 thermal solutions will likely need to design to a value higher than typical power based on the end application, t a target, and i/o power. maximum 4 4 maximum power is based on a voltage of vdd = 1.2 v, worst case process, a junction temperature of t j = 105 c, and an artificial smoke test. unit pbga 266 266 1.3 1.6 1.8 w 133 1.1 1.4 1.6 w 400 266 1.5 1.9 2.1 w 133 1.4 1.7 1.9 w 400 200 1.5 1.8 2.0 w 100 1.3 1.7 1.9 w tbga 333 333 2.0 3.0 3.2 w 166 1.8 2.8 2.9 w 400 266 2.1 3.0 3.3 w 133 1.9 2.9 3.1 w 450 300 2.3 3.2 3.5 w 150 2.1 3.0 3.2 w 500 333 2.4 3.3 3.6 w 166 2.2 3.1 3.4 w 533 266 2.4 3.3 3.6 w 133 2.2 3.1 3.4 w
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 9 power characteristics table 2 shows the typical i/o power dissipation for mpc8347e. table 2. mpc8347e typical i/o power dissipation interface parameter gvdd (2.5 v) ovdd (3.3 v) lvdd (3.3v) lvdd (2.5v) unit comments ddr i/o 65% utilization 2.5 v rs = 20 ? rt = 50 ? 2 pair of clocks 200 mhz, 32 -bit 0.42 w 200 mhz, 64 -bit 0.55 w 266 mhz, 32 -bit 0.5 w 266 mhz, 64 -bit 0.66 w 300 mhz, 32 -bit 0.54 w 300 mhz, 64 -bit 0.7 w 333 mhz, 32 -bit 0.58 w 333 mhz, 64 -bit 0.76 w pci i/o load = 30pf 33 mhz, 32 -bit 0.04 w 66 mhz, 32 -bit 0.07 w local bus i/o load = 25 pf 167 mhz, 32 -bit 0.34 w 133 mhz, 32 -bit 0.27 w 83 mhz, 32 -bit 0.17 w 66 mhz, 32 -bit 0.14 w 50 mhz, 32 -bit 0.11 w tsec i/o load = 25 pf mii 0.01 w mutiply by number of interfaces used. gmii or tbi 0.06 w rgmii or rtbi 0.04 w usb 12 mhz 0.01 w mutiply by 2 if using 2 ports. 480 mhz 0.2 w other i/o 0.01 w
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 10 freescale semiconductor clock input timing 3 clock input timing this section provides the clock input dc and ac electrical characteristics for the mpc8347e. 3.1 dc electrical characteristics table 4 provides the clock input (clkin/pci_sync_in ) dc timing specifications for the mpc8347e. 3.2 ac electrical characteristics the primary clock source for the mpc8347e can be one of two input s, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. table 4 provides the clock input (clkin/pci_clk) ac timing sp ecifications for the mpc8347e. table 3. clkin dc electr ical characteristics parameter condition symbol min max unit input high voltage ? v ih 2.7 ov dd +0.3 v input low voltage ? v il -0.3 0.4 v clkin input current 0v v in ovdd i in ?+/-10 a pci_sync_in input current 0v v in 0.5v or ovdd - 0.5v v in ovdd i in ?+/-10 a pci_sync_in input current 0.5v v in ovdd - 0.5v i in ?+/-50 a table 4. clkin ac timing specifications parameter/condition symbo l min typical max unit notes clkin/pci_clk frequency f clkin ??66mhz1 clkin/pci_clk cycle time t clkin 15 ? ? ns ? clkin/pci_clk rise and fall time t kh , t kl 0.6 1.0 1.2 ns 2 clkin/pci_clk duty cycle t khk /t clkin 40 ? 60 % 3 clkin/pci_clk jitter ? ? ? +/- 150 ps 4, 5 notes: 1. caution: the system, core, usb, security, and tsec must not exceed their respective maximum or minimum operating frequencies. 2. rise and fall times for clkin/pci_clk are measured at 0.4 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. the clkin/pci_clk driver?s closed loop jitter bandwidth should be <500 khz at -20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track clkin drivers with the specified jitter.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 11 reset initialization 4 reset initialization this section describes the dc and ac electrical specifications for the reset initialization timing and electrical requirements of the mpc8347e. 4.1 reset dc electrical characteristics table 5 provides the dc electrical characterist ics for the reset pins of the mpc8347e. 4.2 reset ac electrical characteristics table 6 provides the reset initialization ac timing specifications of the mpc8347e. table 5. reset pins dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih 2.0 ov dd +0.3 v input low voltage v il -0.3 0.8 v input current i in 5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applie s for pins poreset , hreset , sreset and quiesce . 2. hreset and sreset are open drain pins, thus v oh is not relevant for those pins. table 6. reset initializati on timing sp ecifications parameter/condition min max unit notes required assertion time of hreset or sreset (input) to activate reset flow 32 ? t pci_sync_in 1 required assertion time of poreset with stable clock applied to clkin when the mpc8347e is in pci host mode 32 ? t clkin 2 required assertion time of poreset with stable clock applied to pci_sync_in when the mpc8347e is in pci agent mode 32 ? t pci_sync_in 1 hreset /sreset assertion (output) 512 ? t pci_sync_in 1 hreset negation to sreset negation (output) 16 ? t pci_sync_in 1 input setup time for por config signals (cfg_reset_sou rce[0:2] and cfg_clkin_div) with respect to negation of poreset when the mpc8347e is in pci host mode 4?t clkin 2
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 12 freescale semiconductor reset initialization table 7 provides the pll and dll lock times. input setup time for por config signals (cfg_reset_sou rce[0:2] and cfg_clkin_div) with respect to negation of poreset when the mpc8347e is in pci agent mode 4?t pci_sync_in 1 input hold time for por config signals with respect to negation of hreset 0? ns time for the mpc8347e to turn off por config signals with respect to the assertion of hreset ?4 ns3 time for the mpc8347e to turn on por config signals with respect to the negation of hreset 1?t pci_sync_in 1, 3 notes: 1. tpci_sync_in is the clock period of the input clock applied to pci_sync_in. when the mpc8347e is in pci host mode the primary clock is applied to the clkin in put, and pci_sync_in period depends on the value of cfg_clkin_div. see the mpc8349e integrated host processor reference manual rev. 0 for more details. 2. tclkin is the clock period of the input clock applied to cl kin. it is only valid when the mpc8347e is in pci host mode. see the mpc8349e integrated host processor reference manual rev. 0 for more details. 3. por config signals consists of cfg_reset_source[0:2] and cfg_clkin_div. table 7. pll and dll lock times parameter/condition min max unit notes pll lock times ? 100 s dll lock times 7680 122,880 csb_clk cycles 1, 2 notes: 1. dll lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). a 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. the csb_clk is determined by th e clkin and system pll ratio. see section 18, ?clocking ,? for more information. table 6. reset initialization ti ming specifications (continued)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 13 reset initialization
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 14 freescale semiconductor ddr sdram 5 ddr sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the mpc8347e. 5.1 ddr sdram dc electrical characteristics table 8 provides the recommended operating conditions for the ddr sdram component(s) of the mpc8347e. table 9 provides the ddr capacitance. table 8. ddr sdram dc electrical characteristics parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.18 gv dd + 0.3 v input low voltage v il ?0.3 mv ref ? 0.18 v output leakage current i oz ?10 10 a4 output high current (v out = 1.95 v) i oh ?15.2 ? ma output low current (v out = 0.35 v) i ol 15.2 ? ma mv ref input leakage current i vref ?5 a notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 9. ddr sdram capacitance parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf1 delta input/output ca pacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak to peak) = 0.2 v.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 15 ddr sdram 5.2 ddr sdram ac electrical characteristics this section provides the ac electrical ch aracteristics for the ddr sdram interface. 5.2.1 ddr sdram input ac timing specifications table 10 provides the input ac ti ming specifications for the ddr sdram interface. 5.2.2 ddr sdram output ac timing specifications table 11 and table 12 provide the output ac timing specificati ons and measurement conditions for the ddr sdram interface. table 10. ddr sdram input ac timing specifications at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ac input high voltage v ih mv ref + 0.31 gv dd + 0.3 v mdqs?mdq/mecc input skew per byte t diskew ?ps1 333 mhz 750 266 mhz 1125 note: 1. maximum possible skew between a data strobe (mdqs[n]) and any corresponding bit of data (mdq[8n + {0...7}] if 0 <= n <= 7) or ecc (mecc[{0...7}] if n = 8). table 11. ddr sdram output ac timing specifications for source synchronous mode at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes mck[n] cycle time, (mck[n]/mck [n] crossing) t mck 610ns2 skew between any mck to addr/cmd 333 mhz 266 mhz 200 mhz t aoskew -1000 -1100 -1200 200 300 400 ps 3 addr/cmd output setup with respect to mck 333 mhz 266 mhz 200 mhz t ddkhas 2.8 3.45 4.6 ?ns4 addr/cmd output hold with respect to mck 333 mhz 266 mhz 200 mhz t ddkhax 2.0 2.65 3.8 ?ns4
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 16 freescale semiconductor ddr sdram mcs (n) output setup with respect to mck 333 mhz 266 mhz 200 mhz t ddkhcs 2.8 3.45 4.6 ?ns4 mcs (n) output hold with respect to mck 333 mhz 266 mhz 200 mhz t ddkhcx 2.0 2.65 3.8 ?ns4 mck to mdqs 333 mhz 266 mhz 200 mhz t ddkhmh -0.9 -1.1 -1.2 0.3 0.5 0.6 ns 5 mdq/mecc/mdm output setup with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhds, t ddklds 900 900 1200 ?ps6 mdq/mecc/mdm output hold with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhdx, t ddkldx 900 900 1200 ?ps6 table 11. ddr sdram output ac timing specificat ions for source synchr onous mode (c ontinued) at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 17 ddr sdram mdqs preamble start t ddkhmp -0.25 t mck ? 0.9 -0.25 t mck +0.3 ns 7 mdqs epilogue end t ddklme -0.9 0.3 ns 7 notes: 1. the symbols used for timing s pecifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling e dge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a ) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) un til data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. in the source synchronous mode, mck/mck can be shifted in 1/4 applied cycle increments through the clock control register. for the skew measurements referenced for t aoskew it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of mck. 4. addr/cmd includes all ddr sdram output signals except mck/mck , mcs , and mdq/mecc/mdm/mdqs. for the addr/cmd setup and hold specifications, it is assu med that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 5. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck(n) cl ock (kh) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in th e timing_cfg_2 register. in source synchronous mode, this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. see the mpc8349e integrated host processor preliminary reference manual rev.0 for a description and understanding of the timing modifications enabled by use of these bits. 6. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the mpc8347e. 7. all outputs are referenced to the rising edge of mck(n) at the pins of the mpc8347e. note that t ddkhmp follows the symbol conventions described in note 1. table 11. ddr sdram output ac timing specificat ions for source synchr onous mode (c ontinued) at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 18 freescale semiconductor ddr sdram figure 2 shows the ddr sdram output timing for a ddress skew with respect to any mck. figure 2. timing diagram for taoskew measurement figure 3 provides the ac test load for the ddr bus. figure 3. ddr ac test load table 12 shows the ddr sdram measurement conditions. table 12. ddr sdram measurement conditions symbol ddr unit notes v th mv ref 0.31 v v 1 v out 0.5 gv dd v2 notes: 1. data input threshol d measurement point. 2. data output measurement point. addr/cmd mck [n] mck[n] t mck t aoskewmax) cmd noop t aoskew(min) addr/cmd cmd noop output z 0 = 50 ? gv dd /2 r l = 50 ?
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 19 ddr sdram figure 4 shows the ddr sdram output timing di agram for source synchronous mode. figure 4. ddr sdram output timing diagram for source synchronous mode table 13 provides approximate delay info rmation that can be expected for the address and command signals of the ddr controller for va rious loadings, which can be useful for a system utilizing the dll. these numbers are the result of simulations for one topology. the delay numbe rs will strongly depend on the topology used. these delay numbers show the total delay for the addre ss and command to arrive at the dram devices. the actual delay c ould be different than the delays seen in simulation, depending on the system topology. if a heavily loaded system is used, the dll loop may need to be adjusted to meet setup requirements at the dram. table 13. expected delays for address/command load delay unit 4 devices (12 pf) 3.0 ns 9 devices (27 pf) 3.6 ns 36 devices (108 pf) + 40 pf compensation capacitor 5.0 ns 36 devices (108 pf) + 80 pf compensation capacitor 5.2 ns addr/cmd t ddkhas ,t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck [n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax ,t ddkhcx write a0 noop t ddkhme t ddkhmp
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 20 freescale semiconductor duart 6duart this section describes the dc and ac electrical specifications for the duart interface of the mpc8347e. 6.1 duart dc electrical characteristics table 14 provides the dc electrical characteristics for the duart interface of the mpc8347e. 6.2 duart ac electrical specifications table 15 provides the ac timing parameters fo r the duart interface of the mpc8347e. table 15. duart ac timing specifications table 14. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (0.8v v in 2 v) i in ?+/- 5 a high-level output voltage, i oh = ?100 a v oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 a v ol ?0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 6 3 and ta b l e 6 4 . parameter value unit notes minimum baud rate 256 baud maximum baud rate > 1,000,000 baud 1 oversample rate 16 ? 2 notes: 1. actual attainable baud rate will be limited by the latency of interrupt processing. 2. the middle of a start bi t is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. subsequent bit values are sampled each 16 th sample.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 21 duart
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 22 freescale semiconductor ethernet: three-speed ethernet, mii management 7 ethernet: three-speed ethernet, mii management this section provides the ac and dc electrical characteristics for thr ee-speed, 10/100/1000, and mii management. 7.1 three-speed ethernet controller (tsec) (10/100/1000 mbps)?gmii/mii/t bi/rgmii/rtbi electrical characteristics the electrical characteristi cs specified here apply to all gmii (g igabit media independent interface), the mii (media independent interface), tbi (ten-bit in terface), rgmii (reduced gigabit media independent interface), and rtbi (reduced ten-bi t interface) signals ex cept mdio (management data input/output) and mdc (management data clock). the mii, gmii and tbi in terfaces are defi ned for 3.3v, while the rgmii and rtbi interfaces can be operated at 3.3 or 2.5 v. the rgmii and rtbi interfaces follow the hewlett-packard reduced pi n-count interface for gigabit ethernet physical layer de vice specification version 1.2a (9/22/2000). the electrical characte ristics for mdio and mdc are specified in section 7.3, ?ethernet management interf ace electrical characteristics .? 7.1.1 tsec dc electrical characteristics all gmii, mii, tbi, rgmii, and rt bi drivers and receivers comply wi th the dc parametric attributes specified in table 16 and table 17 . the potential applied to the input of a gmii, mii, tbi, rgmii, or rtbi receiver may exceed the potenti al of the receiver?s power supply (i.e., a rgmii driver powered from a 3.6-v supply driving v oh into a rgmii receiver powered from a 2.5-v supply) . tolerance fo r dissimilar rgmii driver and receiver supply potentials is implicit in these specifications. the rgmii and rtbi signals are based on a 2.5-v cmos interface voltage as defined by jedec eia/jesd8-5. table 16. gmii/tbi and mii dc electrical characteristics parameter symbol conditions min max unit supply voltage 3.3 v lv dd 2 ? 2.97 3.63 v output high voltage v oh i oh = ?4.0 ma lv dd = min 2.40 lv dd + 0.3 v output low voltage v ol i ol = 4.0 ma lv dd = min gnd 0.50 v input high voltage v ih ??2.0lv dd + 0.3 v input low voltage v il ? ? ?0.3 0.90 v input high current i ih v in 1 = lv dd ?40 a input low current i il v in 1 = gnd ?600 ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 6 3 and ta b l e 6 4 . 2. gmii/mii pins that are not needed for rgmii or rtbi operation are powered by ovdd supply.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 23 ethernet: three-speed ethernet, mii management 7.2 gmii, mii, tbi, rgmii, an d rtbi ac timing specifications the ac timing specifications for gm ii, mii, tbi, rgmii, and rtbi are presented in this section. 7.2.1 gmii timing specifications this sections describe the gmii transm it and receive ac timing specifications. 7.2.1.1 gmii transmit ac timing specifications table 18 provides the gmii transmit ac timing specifications. table 17. rgmii/rtbi (when operating at 2.5 v), dc electrical characteristics parameters symbol conditions min max unit supply voltage 2.5 v lv dd ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.00 lv dd + 0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd ? 0.3 0.40 v input high voltage v ih ?lv dd = min 1.7 lv dd + 0.3 v input low voltage v il ?lv dd =min ?0.3 0.70 v input high current i ih v in 1 = lv dd ?10 a input low current i il v in 1 = gnd ?15 ? a note: 1. note that the symbol v in , in this case, represents the lv in symbol referenced in ta bl e 6 3 and ta b l e 6 4 . table 18. gmii transmit ac timing specifications at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t gtx ?8.0? ns gtx_clk duty cycle t gtxh /t gtx 40 ? 60 % gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 0.5 ? 5.0 ns gtx_clk clock rise time, v il (min) to v ih (max) t gtxr ??1.0ns gtx_clk clock fall time, v ih (max) to v il (min) t gtxf ??1.0ns
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 24 freescale semiconductor ethernet: three-speed ethernet, mii management figure 5 shows the gmii transm it ac timing diagram. figure 5. gmii transmit ac timing diagram 7.2.1.2 gmii receive ac timing specifications table 19 provides the gmii receiv e ac timing specifications. gtx_clk125 clock period t g125 2 ?8.0? ns gtx_clk125 reference clock duty cycle measured at lv dd / 2 t g125h /t g125 45 ? 55 % notes: 1. the symbols used for timing specif ications herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the cloc k of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this symbol is used to represent the external gtx_clk125 signal and does not follow the original symbol naming convention. table 19. gmii receive ac timing specifications at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk clock period t grx ?8.0? ns rx_clk duty cycle t grxh /t grx 40 ? 60 % rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ? ? ns table 18. gmii transmit ac timing specifications (continued) at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf tx_en tx_er
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 25 ethernet: three-speed ethernet, mii management figure 6 shows the gmii receive ac timing diagram. figure 6. gmii receive ac timing diagram 7.2.2 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 7.2.2.1 mii transmit ac timing specifications table 20 provides the mii transmit ac timing specifications. rx_clk clock rise, v il (min) to v ih (max) t grxr ??1.0ns rx_clk clock fall time, v ih (max) to v il (min) t grxf ??1.0ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data in put signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 20. mii transmit ac timing specifications at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1 5 15 ns table 19. gmii receive ac timing specifications (continued) at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 26 freescale semiconductor ethernet: three-speed ethernet, mii management figure 7 shows the mii transmit ac timing diagram. figure 7. mii transmit ac timing diagram 7.2.2.2 mii receive ac timing specifications table 21 provides the mii receive ac timing specifications. tx_clk data clock rise v il (min) to v ih (max) t mtxr 1.0 ? 4.0 ns tx_clk data clock fall v ih (max) to v il (min) t mtxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit ti ming (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock refere nce symbol representation is based on two to three letters representing the clock of a particular func tional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). table 21. mii receive ac timing specifications at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx ?400? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns table 20. mii transmit ac timing specifications (continued) at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 27 ethernet: three-speed ethernet, mii management figure 8 provides the ac test load for tsec. figure 8. tsec ac test load figure 9 shows the mii receive ac timing diagram. figure 9. mii receive ac timing diagram rx_clk clock rise v il (min) to v ih (max) t mrxr 1.0 ? 4.0 ns rx_clk clock fall time v ih (max) to v il (min) t mrxf 1.0 ? 4.0 ns note: 1. the symbols used for timing specific ations herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data in put signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particul ar functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the la tter convention is used with the appropriate letter: r (rise) or f (fall). table 21. mii receive ac timing specifications (continued) at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit output z 0 = 50 ? lv dd /2 r l = 50 ? rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 28 freescale semiconductor ethernet: three-speed ethernet, mii management 7.2.3 tbi ac timing specifications this section describes the tbi transmit and receive ac ti ming specifications. 7.2.3.1 tbi transmit ac timing specifications table 22 provides the tbi transmit ac timing specifications. figure 10 shows the tbi transmit ac timing diagram. figure 10. tbi transmit ac timing diagram table 22. tbi transmit ac timing specifications at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t ttx ?8.0? ns gtx_clk duty cycle t ttxh /t ttx 40 ? 60 % gtx_clk to tbi data txd[7:0], tx_er, tx_en delay t ttkhdx 0.5 ? 5.0 ns gtx_clk clock rise, v il (min) to v ih (max) t ttxr ??1.0ns gtx_clk clock fall time, v ih (max) to v il (min) t ttxf ??1.0ns gtx_clk125 reference clock period t g125 2 ?8.0? ns gtx_clk125 reference clock duty cycle t g125h /t g125 45 ? 55 ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing ( tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced da ta signals (d) reach the invalid state (x) or hold time. note that, in general, the clock re ference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this symbol is used to represent the external gtx_clk125 and does not follow the original symbol naming convention gtx_clk txd[7:0] t ttx t ttxh t ttxr t ttxf t ttkhdx tx_en tx_er
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 29 ethernet: three-speed ethernet, mii management 7.2.3.2 tbi receive ac timing specifications table 23 provides the tbi receive ac timi ng specifications. figure 11 shows the tbi receive ac timing diagram. figure 11. tbi receive ac timing diagram table 23. tbi receive ac timing specifications at recommended operating conditions with lv dd / ov dd of 3.3 v 10%. parameter/condition symbol 1 min typ max unit pma_rx_clk clock period t trx 16.0 ns pma_rx_clk skew t sktrx 7.5 ? 8.5 ns rx_clk duty cycle t trxh /t trx 40 ? 60 % rxd[7:0], rx_dv, rx_er (rcg[9:0]) setup time to rising pma_rx_clk t trdvkh 2 2.5 ? ? ns rxd[7:0], rx_dv, rx_er (rcg[9:0]) hold time to rising pma_rx_clk t trdxkh 2 1.5 ? ? ns rx_clk clock rise time v il (min) to v ih (max) t trxr 0.7 ? 2.4 ns rx_clk clock fall time v ih (max) to v il (min) t trxf 0.7 ? 2.4 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to t he time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convent ion is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being skewed (trx). 2. setup and hold time of even numbered rcg are meas ured from riding edge of pma_rx_clk1. setup and hold time of odd numbered rcg are measured from riding edge of pma_rx_clk0. pma_rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh pma_rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh even rcg odd rcg
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 30 freescale semiconductor ethernet: three-speed ethernet, mii management 7.2.4 rgmii and rtbi ac timing specifications table 24 presents the rgmii and rt bi ac timing specifications. table 24. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt -0.5 ? 0.5 ns data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock cycle duration 3 t rgt 7.2 8.0 8.8 ns duty cycle for 1000base-t 4, 5 t rgth /t rgt 45 50 55 % duty cycle for 10base-t and 100base-tx 3, 5 t rgth /t rgt 40 50 60 % rise time (20%?80%) t rgtr ? ? 0.75 ns fall time (20%?80%) t rgtf ? ? 0.75 ns gtx_clk125 reference clock period t g12 6 ?8.0?ns gtx_clk125 reference clock duty cycle t g125h /t g125 47 ? 53 % notes: 1. note that, in general, the clock reference symbol repres entation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) time s follows the clock symbol that is being represented. for symbols representing skews, the subscript is skew ( sk) followed by the clock that is being skewed (rgt). 2. this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not viol ated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. duty cycle reference is l vdd /2. 6. this symbol is used to represent the external gtx_clk125 and does not follow the original symbol naming convention.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 31 ethernet: three-speed ethernet, mii management figure 12 shows the rbmii and rtbi ac timing and multiplexing diagrams. figure 12. rgmii and rtbi ac timing and multiplexing diagrams gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 32 freescale semiconductor 7.3 ethernet management interface electrical characteristics the electrical characteristics sp ecified here apply to mii mana gement interface signals mdio (management data input/output) and mdc (management data clock). th e electrical characteristics for gmii, rgmii, tbi and rtbi are specified in section 7.1, ?three-speed ethernet controller (tsec) (10/100/1000 mbps)?gmii/mii /tbi/rgmii/rtbi electrical characteristics .? 7.3.1 mii management dc electrical characteristics the mdc and mdio are defi ned to operate at a supply voltage of 2.5v or 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 25 and table 26 . table 25. mii management dc electrical characteristics when powered at 2.5v parameter symbol conditions min max unit supply voltage (2.5 v) lv dd ? 2.37 2.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.00 lv dd + 0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd - 0.3 0.40 v input high voltage v ih ?lv dd = min 1.7 ? v input low voltage v il ?lv dd = min -0.3 0.70 v input high current i ih v in 1 = lv dd ?10 a input low current i il v in = lv dd -15 ? a note: 1. note that the symbol v in , in this case, represents the lv in symbol referenced in ta bl e 6 3 and ta bl e 6 4 . table 26. mii management dc electrical characteristics when powered at 3.3v parameter symbol conditions min max unit supply voltage (3.3 v) lv dd ? 2.97 3.63 v output high voltage v oh i oh = ?1.0 ma lv dd = min 2.10 lv dd + 0.3 v output low voltage v ol i ol = 1.0 ma lv dd = min gnd 0.50 v input high voltage v ih ?2.00?v input low voltage v il ? ? 0.80 v input high current i ih lv dd = max v in 1 = 2.1 v ? 40 a input low current i il lv dd = max v in = 0.5 v ?600 ? a note: 1. note that the symbol v in , in this case, represents the lv in symbol referenced in ta bl e 6 3 and ta bl e 6 4 .
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 33 7.3.2 mii management ac electrical specifications table 27 provides the mii management ac timing specifications. figure 13 shows the mii management ac timing diagram. figure 13. mii management interface timing diagram table 27. mii management ac timing specifications at recommended operating conditions with lv dd is 3.3 v 10% or 2.5 v 5% parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc ?2.5?mhz2 mdc period t mdc ?400?ns mdc clock pulse width high t mdch 32 ? ? ns mdc to mdio delay t mdkhdx 10 ? 70 ns 3 mdio to mdc setup time t mddvkh 5??ns mdio to mdc hold time t mddxkh 0??ns mdc rise time t mdcr ? ? 10 ns mdc fall time t mdhf ? ? 10 ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a cs b_clk of 375 mhz, the maximum frequency is 11.7 mhz and the minimum frequency is 1.7 mhz). 3. this parameter is dependent on the csb_clk speed (that is , for a csb_clk of 267 mhz, the delay is 70 ns and for a csb_clk of 333 mhz, the delay is 58 ns). mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 34 freescale semiconductor
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 35 usb 8usb this section provides the ac and dc electrical sp ecifications for the usb interface of the mpc8347e. 8.1 usb dc electrical characteristics table 28 provides the dc electrical characteristics for the usb interface. 8.2 usb ac electrical specifications table 29 describes the general timing parameters of the usb interface of the mpc8347e. table 28. usb dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ?5 a high-level output voltage, i oh = ?100 a v oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 a v ol ?0.2v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta bl e 6 3 and ta bl e 6 4 . table 29. usb general timing parameters parameter symbol 1 min max unit notes usb clock cycle time t usck 15 ? ns input setup to usb clock - all inputs t usivkh 4?ns input hold to usb clock - all inputs t usixkh 1?ns
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 36 freescale semiconductor usb figure 14 and figure 15 provide the ac test load and signals for the usb, respectively. figure 14. usb ac test load figure 15. usb signals usb clock to output valid - all outputs t uskhov ?7ns output hold from usb clock - all outputs t uskhox 2?ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t usixkh symbolizes usb timing (us) for the input (i) to go invalid (x) with respect to the time the usb clock reference (k) goes high (h). also, t uskhox symbolizes usb timing (us) for the usb clock reference (k) to go high (h), with respect to the outpu t (o) going invalid (x) or output hold time. 2. all timings are in reference to usb clock. 3. all signals are measured from ov dd /2 of the rising edge of usb clock to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5. for purposes of active/float timing measurem ents, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. table 29. usb general timing parameters (continued) parameter symbol 1 min max unit notes output z 0 = 50 ? ov dd /2 r l = 50 ? output signals: t uskhov usb0_clk/usb1_clk/dr_clk input signals t usixkh t usivkh t uskhox
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 37 local bus 9 local bus this section describes the dc and ac electrical specifications for the local bus interface of the mpc8347e. 9.1 local bus dc electrical characteristics table 30 provides the dc electrical characteristics for the local bus interface. table 30. local bus dc electrical characteristics 9.2 local bus ac electrical specification table 31 and table 32 describe the general timing parameters of the local bus inte rface of the mpc8347e. parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current i in ?5 a high-level output voltage, i oh = ?100 a v oh ov dd ? 0.2 ? v low-level output voltage, i ol = 100 a v ol ?0.2v table 31. local bus general timing parameters?dll on parameter symbol 1 min max unit notes local bus cycle time t lbk 7.5 ? ns 2 input setup to local bus clock (except lupwait) t lbivkh1 1.5 ? ns 3, 4 lupwait input setup to local bus clock t lbivkh2 1.7 ? ns 3, 4 input hold from local bus clock (except lupwait) t lbixkh1 1.0 ? ns 3, 4 lupwait input hold from local bus clock t lbixkh2 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to lale rise t lbkhlr ?4.5ns
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 38 freescale semiconductor local bus local bus clock to output valid (except lad/ldp and lale) t lbkhov1 ?4.5ns local bus clock to data valid for lad/ldp t lbkhov2 ?4.5ns 3 local bus clock to address valid for lad t lbkhov3 ?4.5ns 3 output hold from local bus clock (except lad/ldp and lale) t lbkhox1 1?ns3 output hold from local bus clock for lad/ldp t lbkhox2 1?ns3 local bus clock to output high impedance for lad/ldp t lbkhoz ?3.8ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go inva lid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to rising edge of lsync_in. 3. all signals are measured from ov dd /2 of the rising edge of lsync_in to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5.t lbotot1 should be used when rcwh[lale] is not set and when the load on lale output pin is at least 10pf less than the load on lad output pins. 6.t lbotot2 should be used when rcwh[lale] is set and when the load on lale output pin is at least 10pf less than the load on lad output pins. 7.t lbotot3 should be used when rcwh[lale] is set and when the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing measurem ents, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. table 32. local bus general timing parameters?dll bypass parameter symbol 1 min max unit notes local bus cycle time t lbk 15 ? ns 2 input setup to local bus clock t lbivkh 7 ? ns 3, 4 input hold from local bus clock t lbixkh 1.0 ? ns 3, 4 lale output fall to lad output transition (latch hold time) t lbotot1 1.5 ? ns 5 table 31. local bus general timing parameters?dll on (continued) parameter symbol 1 min max unit notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 39 local bus figure 16 provides the ac test load for the local bus. figure 16. local bus c test load lale output fall to lad output transition (latch hold time) t lbotot2 3?ns6 lale output fall to lad output transition (latch hold time) t lbotot3 2.5 ? ns 7 local bus clock to output valid t lbkhov ?3ns3 local bus clock to output high impedance for lad/ldp t lbkhoz ?4ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go inva lid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to falling edge of lclk0 (for all outputs and for lgta and lupwait inputs) or rising edge of lclk0 (for all other inputs). 3. all signals are measured from ov dd /2 of the rising/falling edge of lclk0 to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 4. input timings are measured at the pin. 5.t lbotot1 should be used when rcwh[lale] is not set and when the load on lale output pin is at least 10pf less than the load on lad output pins. 6.t lbotot2 should be used when rcwh[lale] is set and when the load on lale output pin is at least 10pf less than the load on lad output pins. 7.t lbotot3 should be used when rcwh[lale] is set and when the load on lale output pin equals to the load on lad output pins. 8. for purposes of active/float timing measurem ents, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. dll bypass mode is not recommend ed for use at frequencies above 66mhz. table 32. local bus general timing parameters?dll bypass (continued) parameter symbol 1 min max unit notes output z 0 = 50 ? ov dd /2 r l = 50 ?
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 40 freescale semiconductor local bus figure 17 through figure 22 show the local bus signals. figure 17. local bus signals, nons pecial signals only (dll enabled) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov t lbkhov lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh t lbivkh t lbixkh t lbkhox t lbkhox t lbkhoz t lbkhlr t lbotot t lbkhoz t lbkhox
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 41 local bus figure 18. local bus signals, nonspecial signals only (dll bypass mode) figure 19. local bus signals, gpcm/upm si gnals for lccr[clkdiv] = 2 (dll enabled) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov t lbkhov lclk[n] input signals: lad[0:31]/ldp[0:3] output signals: lad[0:31]/ldp[0:3] t lbixkh t lbivkh t lbkhoz t lbotot lale input signal: lgta t lbixkh t lbivkh t lbixkh lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 42 freescale semiconductor local bus figure 20. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (dll bypass mode) lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz (dll bypass mode)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 43 local bus figure 21. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 (dll bypass mode) lclk upm mode input signal: lupwait t lbixkh t lbivkh t lbivkh t lbixkh t lbkhoz t1 t3 upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov t lbkhov t lbkhoz t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 44 freescale semiconductor local bus figure 22. local bus signals, gpcm/upm si gnals for lccr[clkdiv] = 4 (dll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:3]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:3]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 45 jtag 10 jtag this section describes the dc and ac electrical sp ecifications for the ieee 1149.1 (jtag) interface of the mpc8347e. 10.1 jtag dc electrical characteristics table 33 provides the dc electrical characteristics for the ieee 1149.1 (jtag) interface of the mpc8347e. 10.2 jtag ac timing specifications this section describes the ac el ectrical specifications for the i eee 1149.1 (jtag) interface of the mpc8347e. table 34 provides the jtag ac timing specifications as defined in figure 24 through figure 27 . table 33. jtag interface dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih 2.5 ov dd +0.3 v input low voltage v il -0.3 0.8 v input current i in 5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 34. jtag ac timing specifications (independent of clkin) 1 at recommended operating conditions (see ta b l e 6 4 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 033.3mhz jtag external clock cycle time t jtg 30 ? ns jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns jtag external clock rise and fall times t jtgr & t jtgf 02ns trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 2 2 11 11 ns 5
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 46 freescale semiconductor jtag figure 23 provides the ac test load for tdo and the boundary-scan outputs of the mpc8347e. figure 23. ac test load for the jtag interface figure 24 provides the jtag clock input timing diagram. figure 24. jtag clock input timing diagram output hold times: boundary-scan data tdo t jtkldx t jtklox 2 2 ? ? ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 2 2 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are me asured at the pins. all output timings assume a purely resistive 50- ? load (see figure 23 ). time-of-flight delays must be added for tr ace lengths, vias, and connectors in the system. 2. the symbols used for timing specificat ions herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to th e time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the cloc k reference symbol representation is based on three letters representing the clock of a particular functional. for ri se and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design and characterization. table 34. jtag ac timing specifi cations (independent of clkin) 1 (continued) at recommended operating conditions (see ta b l e 6 4 ). parameter symbol 2 min max unit notes output z 0 = 50 ? ov dd /2 r l = 50 ? jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 47 jtag figure 25 provides the trst timing diagram. figure 25. trst timing diagram figure 26 provides the boundary-scan timing diagram. figure 26. boundary-scan timing diagram figure 27 provides the test access port timing diagram. figure 27. test access port timing diagram trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 48 freescale semiconductor jtag
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 49 i2c 11 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the mpc8347e. 11.1 i 2 c dc electrical characteristics table 35 provides the dc electrical characteristics for the i 2 c interface of the mpc8347e. 11.2 i 2 c ac electrical specifications table 36 provides the ac timing parameters for the i 2 c interface of the mpc8347e . note that all values refer to v ih (min) and v il (max) levels (see table 35 ). table 35. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 10%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v input low voltage level v il ?0.3 0.3 ov dd v low level output voltage v ol 00.2 ov dd v1 output fall time from v ih (min) to v il (max) with a bus capacitance from 10 to 400 pf t i2klkv 20 + 0.1 c b 250 ns 2 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns3 input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a4 capacitance for each i/o pin c i ?10pf notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. c b = capacitance of one bus line in pf. 3. refer to the mpc8349e integrated host processor reference manual rev.0 for information on the digital filter used. 4. i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 36. i 2 c ac electrical specifications parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 1.3 ? s high period of the scl clock t i2ch 0.6 ? s setup time for a repeated start condition t i2svkh 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 0.6 ? s data setup time t i2dvkh 100 ? ns
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 50 freescale semiconductor i2c figure 28 provides the ac test load for the i 2 c. figure 28. i 2 c ac test load data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s rise time of both sda and scl signals t i2cr 20 + 0.1 c b 4 300 ns fall time of both sda and scl signals t i2cf 20 + 0.1 c b 4 300 ns set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specific ations herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input si gnals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. mpc8347e provides a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. table 36. i 2 c ac electrical specifications (continued) parameter symbol 1 min max unit output z 0 = 50 ? ov dd /2 r l = 50 ?
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 51 i2c figure 29 shows the ac timing diagram for the i 2 c bus. figure 29. i 2 c bus ac timing diagram sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 52 freescale semiconductor pci 12 pci this section describes the dc a nd ac electrical specifications for the pci bus of the mpc8347e. 12.1 pci dc electrical characteristics table 37 provides the dc electrical characteristic s for the pci interface of the mpc8347e. 12.2 pci ac electrical specifications this section describes the general ac timing paramete rs of the pci bus of the mpc8347e. note that the pci_clk or pci_sync_in signal is used as the pci input cl ock depending on whether the mpc8347e is configured as a host or agent device. table 38 provides the pci ac timing sp ecifications at 66 mhz. table 37. pci dc electrical characteristics 1 parameter symbol test condition min max unit high-level input voltage v ih v out v oh (min) or 2 ov dd + 0.3 v low-level input voltage v il v out v ol (max) ?0.3 0.8 v input current i in v in 2 = 0 v or v in = v dd ?5 a high-level output voltage v oh ov dd = min, i oh = ?100 a ov dd ? 0.2 ? v low-level output voltage v ol ov dd = min, i ol = 100 a ?0.2v notes: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 6 3 and ta b l e 6 4 . table 38. pci ac timing specifications at 66 mhz 6 parameter symbol 1 min max unit notes clock to output valid t pckhov ?6.0ns2 output hold from clock t pckhox 1?ns2 clock to output high impedance t pckhoz ?14ns2, 3
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 53 pci table 39 provides the pci ac timing specifications at 33 mhz. input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0 ? ns 2, 4 notes: 1. note that the symbols used for timing spec ifications herein fo llow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the ti me the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. 6. pci timing depends on m66en and the ratio between pci1/p ci2. refer to user manual, pci chapter, description of m66en paragraph. table 39. pci ac timing specifications at 33 mhz parameter symbol 1 min max unit notes clock to output valid t pckhov ?11ns2 output hold from clock t pckhox 2?ns2 clock to output high impedance t pckhoz ?14ns2, 3 input setup to clock t pcivkh 3.0 ? ns 2, 4 input hold from clock t pcixkh 0 ? ns 2, 4 notes: 1. note that the symbols used for timing spec ifications herein fo llow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the ti me the input signals (i) reach the valid state (v) relative to the pci_sync_in clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. table 38. pci ac timing specifications at 66 mhz 6 (continued) parameter symbol 1 min max unit notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 54 freescale semiconductor pci figure 30 provides the ac test load for pci. figure 30. pci ac test load figure 31 shows the pci input ac timing diagram. figure 31. pci input ac timing diagram figure 32 shows the pci output ac timing diagram. figure 32. pci output ac timing diagram output z 0 = 50 ? ov dd /2 r l = 50 ? t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output t pckhox
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 55 timers 13 timers this section describes the dc a nd ac electrical specifications for the timers of the mpc8347e. 13.1 timers dc electrical characteristics table 40 provides the dc electrical characteristics for the mpc8347e timers pi ns, including tin, tout , tgate and rtc_clk. 13.2 timers ac timing specifications table 41 provides the timers input and output ac t iming specifications. table 40. timers dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih 2.0 ov dd +0.3 v input low voltage v il -0.3 0.8 v input current i in 5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 41. timers input ac timing specifications 1 characteristic symbol 2 min unit timers inputs?minimum pulse width t tiwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2.timers inputs and outputs are asynchronous to any visibl e clock. timers outputs should be synchronized before use by any external synchronous logic. timers inputs are required to be valid for at least t tiwid ns to ensure proper operation.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 56 freescale semiconductor gpio 14 gpio this section describes the dc a nd ac electrical specifications for the gpio of the mpc8347e. 14.1 gpio dc electrical characteristics table 42 provides the dc electrical charac teristics for the mpc8347e gpio. 14.2 gpio ac timing specifications table 43 provides the gpio i nput and output ac ti ming specifications. table 42. gpio dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih 2.0 ov dd +0.3 v input low voltage v il -0.3 0.8 v input current i in 5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 43. gpio input ac timing specifications 1 characteristic symbol 2 min unit gpio inputs?minimum pulse width t piwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2.gpio inputs and outputs are asynchronous to any visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio i nputs are required to be valid for at least t piwid ns to ensure proper operation.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 57 ipic 15 ipic this section describes the dc and ac electrical specifications for the external interrupt pins of the mpc8347e. 15.1 ipic dc electrical characteristics table 44 provides the dc electrical char acteristics for the external in terrupt pins of the mpc8347e. 15.2 ipic ac timing specifications table 45 provides the ipic input and output ac timing specifications. table 44. ipic dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih 2.0 ov dd +0.3 v input low voltage v il -0.3 0.8 v input current i in 5 a output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v notes: 1. this table applies for pins irq [0:7], irq_out and mcp_out . 2. irq_out and mcp_out are open drain pins, thus v oh is not relevant for those pins. table 45. ipic input ac timing specifications 1 characteristic symbol 2 min unit ipic inputs?minimum pulse width t picwid 20 ns notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2.ipic inputs and outputs are asynchronous to any visible clock. ipic outputs should be synchronized before use by any external synchronous logic. ipic inpu ts are required to be valid for at least t picwid ns to ensure proper operation when working in edge triggered mode.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 58 freescale semiconductor spi 16 spi this section describes the dc and ac electric al specifications for the spi of the mpc8347e. 16.1 spi dc electrical characteristics table 46 provides the dc electrical charac teristics for the mpc8347e spi. 16.2 spi ac timing specifications table 47 and provide the spi input and output ac timing specifications. table 46. spi dc electrical characteristics characteristic symbol condition min max unit input high voltage v ih 2.0 ov dd +0.3 v input low voltage v il -0.3 0.8 v input current i in 5 a output high voltage v oh i oh = ?8.0 ma 2.4 ? v output low voltage v ol i ol = 8.0 ma ? 0.5 v output low voltage v ol i ol = 3.2 ma ? 0.4 v table 47. spi ac timing specifications 1 characteristic symbol 2 min max unit spi outputs valid?master mode (internal clock) delay t nikhov 6ns spi outputs hold?master mode (internal clock) delay t nikhox 0.5 ns spi outputs valid?slave mode (external clock) delay t nekhov 8ns spi outputs hold?slave mode (external clock) delay t nekhox 2ns spi inputs?master mode (internal clock input setup time t niivkh 4ns spi inputs?master mode (internal clock input hold time t niixkh 0ns spi inputs?slave mode (external clock) input setup time t neivkh 4ns spi inputs?slave mode (external clock) input hold time t neixkh 2ns notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhox symbolizes the internal timing (ni) for the time spiclk clock reference (k) goes to the high state (h) until outputs (o) are invalid (x).
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 59 spi figure 33 provides the ac test load for the spi. figure 33. spi ac test load figure 34 through figure 35 represent the ac timing from table 47 . note that although the specifications generally reference the risi ng edge of the clock, these ac timing diag rams also apply when the falling edge is the active edge. figure 34 shows the spi timing in sl ave mode (external clock). figure 34. spi ac timing in slave mode (external clock) diagram figure 35 shows the spi timing in mast er mode (internal clock). figure 35. spi ac timing in master mode (internal clock) diagram output z 0 = 50 ? ov dd /2 r l = 50 ? spiclk (input) t neixkh t neivkh t nekhox input signals: spimosi (see note) output signals: spimiso (see note) note: the clock edge is selectable on spi. spiclk (output) t niixkh t nikhox input signals: spimiso (see note) output signals: spimosi (see note) note: the clock edge is selectable on spi. t niivkh
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 60 freescale semiconductor package and pin listings 17 package and pin listings this section details package parameters, pin assignm ents, and dimensi ons. the mpc8347e is available in two packages a tape ball grid array (tbga) and a plastic ball gr id array (pbga), see section 17.1, ?package parameters for the mpc8347e tbga ,? and section 17.2, ?mechanical dimensions of the mpc8347e tbga ,?for information on the tbga.and section 17.3, ?package parameters for the mpc8347e pbga ,?and section 17.4, ?mechani cal dimensions of the mpc8347e pbga ,? on the pbga. 17.1 package parameters for the mpc8347e tbga the package parameters are as provided in th e following list. the package type is 35 mm 35 mm, 672 tape ball grid array (tbga). package outline 35 mm 35 mm interconnects 672 pitch 1.00 mm module height (typical) 1.46 mm solder balls 62 sn/36 pb/2 ag (zu package) 95.5 sn/0.5 cu/4ag (vv package) ball diameter (typical) 0.64 mm
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 61 package and pin listings 17.2 mechanical dimensions of the mpc8347e tbga figure 36 the mechanical dimensions and bottom surface nomenclature of the mpc8347e, 672-tbga package. figure 36. mechanical dimensions and bottom surface nomenclature of the mpc8347e tbga notes 1. all dimensions are in millimeters. 2. dimensions and tolera nces per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is determined by the spherical crowns of the solder balls . 5. parallelism measurement must exclude any effect of mark on top surface of package.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 62 freescale semiconductor package and pin listings 17.3 package parameters for the mpc8347e pbga the package parameters are as provided in th e following list. the package type is 29 mm 29 mm, 620 plastic ball grid array (pbga). package outline 29 mm 29 mm interconnects 620 pitch 1.00 mm module height (maximum) 2.46 mm module height (typical) 2.23 mm module height (minimum) 2.00 mm solder balls 62 sn/36 pb/2 ag (zq package) 95.5 sn/0.5 cu/4ag (vr package) ball diameter (typical) 0.60 mm
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 63 package and pin listings 17.4 mechanical dimensions of the mpc8347e pbga figure 37 the mechanical dimensions and bottom surface nomenclature of the mpc8347e, 620-pbga package. figure 37. mechanical dimensions and bottom surface nomenclature of the mpc8347e pbga note 1. all dimensions in millimeters 2. dimensioning and tolerancing per asme y14. 5m-1994
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 64 freescale semiconductor package and pin listings 3. maximum solder ball diameter measured parallel to datum a datum a, the seating plane, is determined by the spherical crowns of the solder balls.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 65 17.5 pinout listings table 48 provides the pin-out listing fo r the mpc8347e, 672 tbga package. table 48. mpc8347e (tbga) pinout listing signal package pin number pin type power supply notes pci pci_inta /irq_out b34 o ov dd 2 pci_reset_out c33 o ov dd pci_ad[31:0] g30, g32, g34, h31, h32, h33, h34, j29, j32, j33, l30, k31, k33, k34, l33, l34, p34, r29, r30, r33, r34, t31, t32, t33, u31, u34, v31, v32, v33, v34, w33, w34 i/o ov dd pci_c/be [3:0] j30, m31, p33, t34 i/o ov dd pci_par p32 i/o ov dd pci_frame m32 i/o ov dd 5 pci_trdy n29 i/o ov dd 5 pci_irdy m34 i/o ov dd 5 pci_stop n31 i/o ov dd 5 pci_devsel n30 i/o ov dd 5 pci_idsel j31 i ov dd pci_serr n34 i/o ov dd 5 pci_perr n33 i/o ov dd 5 pci_req [0] d32 i/o ov dd pci_req [1]/cpci1_hs_es d34 i ov dd pci_req [2:4] e34, f32, g29 i ov dd pci_gnt 0 c34 i/o ov dd pci_gnt 1/cpci1_hs_led d33 o ov dd pci_gnt 2/ cpci1_hs_enum e33 o ov dd pci _gnt [3:4] f31, f33 o ov dd m66en a19 i ov dd ddr sdram memory interface mdq[0:63] d5, a3, c3, d3, c4 , b3, c2, d4, d2, e5, g2, h6, e4, f3, g4, g3, h1, j2, l6, m6, h2, k6, l2, m4, n2, p4, r2, t4, p6, p3, r1, t2, ab5, aa3, ad6, ae4, ab4, ac2, ad3, ae6, ae3, ag4, ak5, ak4, ae2, ag6, ak3, ak2, al2, al1, am5, ap5, am2, an1, ap4, an5, aj7, an7, am8, aj9, ap6, al7, al9, an8 i/o gv dd
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 66 freescale semiconductor mecc[0:4]/msrcid[0:4] w4, w3, y3, aa6, t1 i/o gv dd mecc[5]/mdval u1 i/o gv dd mecc[6:7] y1, y6 i/o gv dd mdm[0:8] b1, f1, k1, r4, ad4, aj1, ap3, ap7, y4 o gv dd mdqs[0:8] b2, f5, j1, p2, ac1, aj2, an4, al8, w2 i/o gv dd mba[0:1] ad1, aa5 o gv dd ma[0:14] w1, u4, t3, r3, p1 , m1, n1, l3, l1, k2, y2, k3, j3, ap2, an6 ogv dd mwe af1 o gv dd mras af4 o gv dd mcas ag3 o gv dd mcs [0:3] ag2, ag1, ak1, al4 o gv dd mcke[0:1] h3, g1 o gv dd 3 mck[0:5] u2, f4, am3, v3, f2, an3 o gv dd mck [0:5] u3, e3, an2, v4, e1, am4 o gv dd local bus controller interface lad[0:31] am13, ap13, a l14, am14, an14, ap14, ak15, aj15, am15, an15, ap15, am16, al16, an16, ap16, al17, am17, ap17, ak17, ap18, al18, am18, an18, ap19, an19, am19, ap20, ak19, an20, al20, ap21, an21 i/o ov dd ldp[0]/ckstop_out am21 i/o ov dd ldp[1]/ckstop_in ap22 i/o ov dd ldp[2] an22 i/o ov dd ldp[3] am22 i/o ov dd la[27:31] ak21, ap23, an23, ap24, ak22 o ov dd lcs [0:3] an24, al23, ap25, an25 o ov dd lwe [0:3]/lsddqm[0:3]/ lbs[0:3] ak23, ap26, al24, am25 o ov dd lbctl an26 o ov dd lale ak24 o ov dd lgpl0/lsda10/ cfg_reset_source0 ap27 i/o ov dd table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 67 lgpl1/lsdwe/ cfg_reset_source1 al25 i/o ov dd lgpl2/ lsdras /loe aj24 o ov dd lgpl3/lsdcas/ cfg_reset_source2 an27 i/o ov dd lgpl4/lgta /lupwait/lpbse ap28 i/o ov dd lgpl5/cfg_clkin_div al26 i/o ov dd lcke am27 o ov dd lclk[0:2] an28, ak26, ap29 o ov dd lsync_out am12 o ov dd lsync_in aj10 i ov dd general purpose i/o timers gpio1[0]/ gtm1_tin1/ gtm2_tin2 f24 i/o ov dd gpio1[1]/ gtm1_tgate1 / gtm2_tgate2 e24 i/o ov dd gpio1[2]/ gtm1_tout1 b25 i/o ov dd gpio1[3]/ gtm1_tin2/ gtm2_tin1 d24 i/o ov dd gpio1[4]/ gtm1_tgate2 / gtm2_tgate1 a25 i/o ov dd gpio1[5]/ gtm1_tout2 / gtm2_tout1 b24 i/o ov dd gpio1[6]/ gtm1_tin3/ gtm2_tin4 a24 i/o ov dd gpio1[7]/ gtm1_tgate3 / gtm2_tgate4 d23 i/o ov dd gpio1[8]/ gtm1_tout3 b23 i/o ov dd table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 68 freescale semiconductor gpio1[9]/ gtm1_tin4/ gtm2_tin3 a23 i/o ov dd gpio1[10]/ gtm1_tgate4 / gtm2_tgate3 f22 i/o ov dd gpio1[11]/ gtm1_tout4 / gtm2_tout3 e22 i/o ov dd usb port 1 mph1_d0_enablen/dr_d0_ enablen a26 i/o ov dd mph1_d1_ser_txd/dr_d1_ ser_txd b26 i/o ov dd mph1_d2_vmo_se0/dr_d2_ vmo_se0 d25 i/o ov dd mph1_d3_speed/dr_d3_sp eed a27 i/o ov dd mph1_d4_dp/dr_d4_dp b27 i/o ov dd mph1_d5_dm/dr_d5_dm c27 i/o ov dd mph1_d6_ser_rcv/dr_d6_ ser_rcv d26 i/o ov dd mph1_d7_drvvbus/dr_d7_ drvvbus e26 i/o ov dd mph1_nxt/dr_sess_vld_n xt d27 i ov dd mph1_dir_dppullup/ dr_xcvr_sel_dppullup a28 i/o ov dd mph1_stp_suspend/dr_st p_suspend f26 o ov dd mph1_pwrfault/ dr_rx_error_pwrfault e27 i ov dd mph1_pctl0/dr_tx_valid_ pctl0 a29 o ov dd mph1_pctl1/dr_tx_validh _pctl1 d28 o ov dd mph1_clk/dr_clk b29 i ov dd table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 69 usb port 0 mph0_d0_enablen/ dr_d8_chgvbus c29 i/o ov dd mph0_d1_ser_txd/ dr_d9_dchgvbus a30 i/o ov dd mph0_d2_vmo_se0/ dr_d10_dppd e28 i/o ov dd mph0_d3_speed/ dr_d11_dmmd b30 i/o ov dd mph0_d4_dp/ dr_d12_vbus_vld c30 i/o ov dd mph0_d5_dm/ dr_d13_sess_end a31 i/o ov dd mph0_d6_ser_rcv/dr_d14 b31 i/o ov dd mph0_d7_drvvbus/dr_d15 _idpullup c31 i/o ov dd mph0_nxt/ dr_rx_active_id b32 i ov dd mph0_dir_dppullup/ dr_reset a32 i/o ov dd mph0_stp_suspend/ dr_tx_ready a33 i/o ov dd mph0_pwrfault/ dr_rx_validh c32 i ov dd mph0_pctl0/ dr_line_state0 d31 i/o ov dd mph0_pctl1/ dr_line_state1 e30 i/o ov dd mph0_clk/ dr_rx_valid b33 i ov dd programmable interrupt controller mcp_out an33 o ov dd 2 irq 0/mcp_in/ gpio2[12] c19 i/o ov dd irq [1:5]/gpio2[13:17] c22, a22, d21, c21, b21 i/o ov dd irq [6]/gpio2[18]/ ckstop_out a21 i/o ov dd irq [7]/gpio2[19]/ ckstop_in c20 i/o ov dd table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 70 freescale semiconductor ethernet management interface ec_mdc a7 o lv dd1 ec_mdio e9 i/o lv dd1 2 gigabit reference clock ec_gtx_clk125 c8 i lv dd1 three-speed ethernet contro ller (gigabit ethernet 1) tsec1_col/ gpio2[20] a17 i/o ov dd tsec1_crs/ gpio2[21] f12 i/o lv dd1 tsec1_gtx_clk d10 o lv dd1 3 tsec1_rx_clk a11 i lv dd1 tsec1_rx_dv b11 i lv dd1 tsec1_rx_er/ gpio2[26] b17 i/o ov dd tsec1_rxd[7:4]/ gpio2[22:25] b16, d16, e16, f16 i/o ov dd tsec1_rxd[3:0] e 10, a8, f10, b8 i lv dd1 tsec1_tx_clk d17 i ov dd tsec1_txd[7:4]/ gpio2[27:30] a15, b15, a14, b14 i/o ov dd tsec1_txd[3:0] a10, e11, b10, a9 o lv dd1 tsec1_tx_en b9 o lv dd1 tsec1_tx_er/ gpio2[31] a16 i/o ov dd three-speed ethernet contro ller (gigabit ethernet 2) tsec2_col/ gpio1[21] c14 i/o ov dd tsec2_crs/ gpio1[22] d6 i/o lv dd2 tsec2_gtx_clk a4 o lv dd2 tsec2_rx_clk b4 i lv dd2 tsec2_rx_dv/ gpio1[23] e6 i/o lv dd2 tsec2_rxd[7:4]/ gpio1[26:29] a13, b13, c13, a12 i/o ov dd tsec2_rxd[3:0]/ gpio1[13:16] d7, a6, e8, b7 i/o lv dd2 tsec2_rx_er/ gpio1[25] d14 i/o ov dd tsec2_txd[7]/ gpio1[31] b12 i/o ov dd tsec2_txd[6]/ dr_xcvr_term_sel c12 o ov dd table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 71 tsec2_txd[5]/ dr_utmi_opmode1 d12 o ov dd tsec2_txd[4]/ dr_utmi_opmode0 e12 o ov dd tsec2_txd[3:0]/ gpio1[17:20] b5, a5, f8, b6 i/o lv dd2 tsec2_tx_er/ gpio1[24] f14 i/o ov dd tsec2_tx_en/ gpio1[12] c5 i/o lv dd2 3 tsec2_tx_clk/ gpio1[30] e14 i/o ov dd duart uart_sout[1:2]/ msrcid[0:1]/lsrcid[0:1] ak27, an29 o ov dd uart_sin[1:2]/ msrcid[2:3]/lsrcid[2:3] al28, am29 i/o ov dd uart_cts [1]/ msrcid4/lsrcid4 ap30 i/o ov dd uart_cts [2]/ mdval/ ldval an30 i/o ov dd uart_rts [1:2] ap31, am30 o ov dd i 2 c interface iic1_sda ak29 i/o ov dd 2 iic1_scl ap32 i/o ov dd 2 iic2_sda an31 i/o ov dd 2 iic2_scl am31 i/o ov dd 2 spi spimosi an32 i/o ov dd spimiso ap33 i/o ov dd spiclk ak30 i/o ov dd spisel al31 i ov dd clocks pci_clk_out[0:4] an9, ap9, am10, an10, aj11 o ov dd pci_sync_in/pci_clock ak12 i ov dd pci_sync_out ap11 o ov dd 3 rtc/pit_clock am32 i ov dd table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 72 freescale semiconductor clkin am9 i ov dd jtag tck e20 i ov dd tdi f20 i ov dd 4 tdo b20 o ov dd 3 tms a20 i ov dd 4 trst b19 i ov dd 4 test test d22 i ov dd 6 test_sel al13 i ov dd 7 pmc quiesce a18 o ov dd system control poreset c18 i ov dd hreset b18 i/o ov dd 1 sreset d18 i/o ov dd 2 thermal management therm0 k32 i ?9 power and ground signals av dd 1 l31 power for e300 pll (1.2 v) av dd 1 av dd 2ap12 power for system pll (1.2 v) av dd 2 av dd 3 ae1 power for ddr dll (1.2 v) av dd 3 av dd 4aj13 power for lbiu dll (1.2 v) av dd 4 table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 73 gnd a1, a34, c1, c7, c10, c11, c15, c23, c25, c28, d1, d8, d20, d30, e7, e13, e15, e17, e18, e21, e23, e25, e32, f6, f19, f27, f30, f34, g31, h5, j4, j34, k30, l5, m2, m5, m30, m33, n3, n5, p30, r5, r32, t5, t30, u6, u29, u33, v2, v5, v30, w6, w30, y30, aa2, aa30, ab2, ab6, ab30, ac3, ac6, ad31, ae5, af2, af5, af31, ag30, ag31, ah4, aj3, aj19, aj22, ak7, ak13, ak14, ak16, ak18, ak20, ak25, ak28, al3, al5, al10, al12 , al22, al27, am1, am6, am7, an12, an17, an34, ap1, ap8, ap34 ?? gv dd a2, e2, g5, g6, j5, k4, k5, l4, n4, p5, r6, t6, u5, v1, w5, y5, aa4, ab3, ac4, ad5, af3, ag5, ah2, ah5, ah6, aj6, ak6, ak8, ak9, al6 power for ddr dram i/o voltage (2.5 v) gv dd lv dd1 c9, d11 power for three speed ethernet #1 and for ethernet management interface i/o (2.5v, 3.3v) lv dd1 lv dd2 c6, d9 power for three speed ethernet #2 i/o (2.5v, 3.3v) lv dd2 v dd e19, e29, f7, f9, f11, f13, f15, f17, f18, f21, f23, f25, f29, h 29, j6, k29, m29, n6, p29, t29, u30, v6, v29, w29, ab29, ac5, ad29, af6, af29, ah29, aj8, aj12, aj14, aj16, aj18, aj20, aj21, aj23, aj25, aj26, aj27, aj28, aj29, ak10 power for core (1.2 v) v dd ov dd b22, b28, c16, c17, c24, c26, d13, d15, d19, d29, e31, f28, g33, h30, l29, l32, n32, p31, r31, u32, w31, y29, aa29, ac30, ae31, af30, ag29, aj17, aj30, ak11, al15, al19, al21, al29, al30, am20, am23, am24, am26, am28, an11, an13 pci, 10/100 ethernet, and other standard (3.3 v) ov dd mvref1 m3 i ddr reference voltage mvref2 ad2 i ddr reference voltage table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 74 freescale semiconductor pins reserved for future ddr2 (they should be left unconnected for 8347) odt[0:3] ah3, aj5, ah1, aj4 ? ? mba[2] h4 ? ? no connection nc w32, aa31, aa32, aa33, aa34, ab31, ab32, ab33, ab34, ac29, ac31, ac33, ac34, ad30, ad32, ad33, ad34, ae29, ae30, ah32, ah33, ah34, am33, aj31, aj32, aj33, aj34, ak32, ak33, ak34, am34, al33, al34, ak31, ah30, ac32, ae32, ah31, al32, ag34, ae33, af32, ae34, af34, af33, ag33, ag32, al11, am11, ap10, y32, y34, y31, y33 ?? spare1 aa1 ? ? 8 spare2 ab1 ? ? 6 notes: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ? ) should be placed on this pin to ov dd 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ? ) should be placed on this pin to ov dd . 3. this output is actively driven during reset rather than being three-stated during reset. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull up if the chip is in pci host mode. follow pci specifications recommendation. 6. this pin must always be tied to gnd 7. this pin must always be pulled up to ov dd 8. this pin must always be left not connected. 9. thermal sensitive resistor. table 48. mpc8347e (tbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 75 table 49 provides the pin-out listing fo r the mpc8347e, 620 pbga package. table 49. mpc8347e (pbga) pinout listing signal package pin number pin type power supply notes pci pci1_inta /irq_out d20 o ov dd 2 pci1_reset_out b21 o ov dd pci1_ad[31:0] e19, d 17, a16, a18, b17, b16, d16, b18, e17, e16, a15, c16, d15, d14, c14, a12, d12, b11, c11, e12, a10, c10, a9, e11, e10, b9, b8, d9, a8, c9, d8, c8 i/o ov dd pci1_c/be [3:0] a17, a14, a11, b10 i/o ov dd pci1_par d13 i/o ov dd pci1_frame b14 i/o ov dd 5 pci1_trdy a13 i/o ov dd 5 pci1_irdy e13 i/o ov dd 5 pci1_stop c13 i/o ov dd 5 pci1_devsel b13 i/o ov dd 5 pci1_idsel c17 i ov dd pci1_serr c12 i/o ov dd 5 pci1_perr b12 i/o ov dd 5 pci1_req [0] a21 i/o ov dd pci1_req [1]/ cpci1_hs_es c19 i ov dd pci1_req [2:4] c18, a19, e20 i ov dd pci1_gnt 0b20 i/o ov dd pci1_gnt 1/ cpci1_hs_led c20 o ov dd pci1_gnt 2/ cpci1_hs_enum b19 o ov dd pci1 _gnt [3:4] a20, e18 o ov dd m66en l26 i ov dd
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 76 freescale semiconductor ddr sdram memory interface mdq[0:63] ac25, ad27, ad 25, ah27, ae28, ad26, ad24, af27, af25, af28, ah24, ag26, ae25, ag25, ah26, ah25, ag22, ah22, ae21, ad19, ae22, af23, ae19, ag20, ag19, ad17, ae16, af16, af18, ag18, ah17, ah16, ag9, ad12, ag7, ae8, ad11, ah9, ah8, af6, af8, ae6, af1, ae4, ag8, ah3, ag3, ag4, ah2, ad7, ab4, ab3, ag1, ad5, ac2, ac1, ac4, aa3, y4, aa4, ab1, ab2, y5, y3 i/o gv dd mecc[0:4]/msrcid[0:4] ag13, ae14, ah12, ah10, ae15 i/o gv dd mecc[5]/mdval ah14 i/o gv dd mecc[6:7] ae13, ah11 i/o gv dd mdm[0:8] ag28, ag24, af20, ag17, ae9, ah5, ad1, aa2, ag12 ogv dd mdqs[0:8] ae27, ae26, ae20, ah18, ag10, af5, ac3, aa1, ah13 i/o gv dd mba[0:1] af10, af11 o gv dd ma[0:14] af13, af15, ag 16, ad16, af17, ah20, ah19, ah21, ad18, ag21, ad13, af21, af22, ae1, aa5 ogv dd mwe ad10 o gv dd mras af7 o gv dd mcas ag6 o gv dd mcs [0:3] ae7, ah7, ah4, af2 o gv dd mcke[0:1] ag23, ah23 o gv dd 3 mck[0:5] ah15, ae24, ae2, af14, ae23, ad3 o gv dd mck [0:5] ag15, ad23, ae3, ag14, af24, ad2 o gv dd local bus controller interface lad[0:31] t4, t5, t1, r2, r3 , t2, r1, r4, p1, p2, p3, p4, n1, n4, n2, n3, m1, m2, m3, n5, m4, l1, l2, l3, k1, m5, k2, k3, j1, j2, l5, j3 i/o ov dd ldp[0]/ckstop_out h1 i/o ov dd ldp[1]/ckstop_in k5 i/o ov dd ldp[2] h2 i/o ov dd ldp[3] g1 i/o ov dd table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 77 la[27:31] j4, h3, g2, f1, g3 o ov dd lcs [0:3] j5, h4, f2, e1 o ov dd lwe [0:3]/lsddqm[0:3]/ lbs[0:3] f3, g4, d1, e2 o ov dd lbctl h5 o ov dd lale e3 o ov dd lgpl0/lsda10/ cfg_reset_source0 f4 i/o ov dd lgpl1/lsdwe/ cfg_reset_source1 d2 i/o ov dd lgpl2/ lsdras /loe c1 o ov dd lgpl3/lsdcas/ cfg_reset_source2 c2 i/o ov dd lgpl4/lgta /lupwait/lpbse c3 i/o ov dd lgpl5/cfg_clkin_div b3 i/o ov dd lcke e4 o ov dd lclk[0:2] d4, a3, c4 o ov dd lsync_out u3 o ov dd lsync_in y2 i ov dd general purpose i/o timers gpio1[0]/ gtm1_tin1/ gtm2_tin2 d27 i/o ov dd gpio1[1]/ gtm1_tgate1 / gtm2_tgate2 e26 i/o ov dd gpio1[2]/ gtm1_tout1 d28 i/o ov dd gpio1[3]/ gtm1_tin2/ gtm2_tin1 g25 i/o ov dd gpio1[4]/ gtm1_tgate2 / gtm2_tgate1 j24 i/o ov dd gpio1[5]/ gtm1_tout2 / gtm2_tout1 f26 i/o ov dd table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 78 freescale semiconductor gpio1[6]/ gtm1_tin3/ gtm2_tin4 e27 i/o ov dd gpio1[7]/ gtm1_tgate3 / gtm2_tgate4 e28 i/o ov dd gpio1[8]/ gtm1_tout3 h25 i/o ov dd gpio1[9]/ gtm1_tin4/ gtm2_tin3 f27 i/o ov dd gpio1[10]/ gtm1_tgate4 / gtm2_tgate3 k24 i/o ov dd gpio1[11]/ gtm1_tout4 / gtm2_tout3 g26 i/o ov dd usb port 1 mph1_d0_enablen/dr_d0_ enablen c28 i/o ov dd mph1_d1_ser_txd/dr_d1_ ser_rxd f25 i/o ov dd mph1_d2_vmo_se0/dr_d2_ vmo_se0 b28 i/o ov dd mph1_d3_speed/dr_d3_sp eed c27 i/o ov dd mph1_d4_dp/dr_d4_dp d26 i/o ov dd mph1_d5_dm/dr_d5_dm e25 i/o ov dd mph1_d6_ser_rcv/dr_d6_ ser_rcv c26 i/o ov dd mph1_d7_drvvbus/dr_d7_ drvvbus d25 i/o ov dd mph1_nxt/dr_sess_vld_n xt b26 i ov dd mph1_dir_dppullup/ dr_xcvr_sel_dppullup e24 i/o ov dd mph1_stp_suspend/dr_st p_suspend a27 o ov dd mph1_pwrfault/ dr_rx_error_pwrfault c25 i ov dd table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 79 mph1_pctl0/dr_tx_valid_ pctl0 a26 o ov dd mph1_pctl1/dr_tx_validh _pctl1 b25 o ov dd mph1_clk/dr_clk a25 i ov dd usb port 0 mph0_d0_enablen/ dr_d8_chgvbus d24 i/o ov dd mph0_d1_ser_txd/ dr_d9_dchgvbus c24 i/o ov dd mph0_d2_vmo_se0/ dr_d10_dppd b24 i/o ov dd mph0_d3_speed/ dr_d11_dmmd a24 i/o ov dd mph0_d4_dp/ dr_d12_vbus_vld d23 i/o ov dd mph0_d5_dm/ dr_d13_sess_end c23 i/o ov dd mph0_d6_ser_rcv/dr_d14 b23 i/o ov dd mph0_d7_drvvbus/dr_d15 _idpullup a23 i/o ov dd mph0_nxt/ dr_rx_active_id d22 i ov dd mph0_dir_dppullup/ dr_reset c22 i/o ov dd mph0_stp_suspend/ dr_tx_ready b22 i/o ov dd mph0_pwrfault/ dr_rx_validh a22 i ov dd mph0_pctl0/ dr_line_state0 e21 i/o ov dd mph0_pctl1/ dr_line_state1 d21 i/o ov dd mph0_clk/ dr_rx_valid c21 i ov dd programmable interrupt controller mcp_out e8 o ov dd 2 irq 0/mcp_in/ gpio2[12] j28 i/o ov dd table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 80 freescale semiconductor irq [1:5]/gpio2[13:17] k25, j25, h26, l24, g27 i/o ov dd irq [6]/gpio2[18]/ ckstop_out g28 i/o ov dd irq [7]/gpio2[19]/ ckstop_in j26 i/o ov dd ethernet management interface ec_mdc y24 o lv dd1 ec_mdio y25 i/o lv dd1 2 gigabit reference clock ec_gtx_clk125 y26 i lv dd1 three-speed ethernet contro ller (gigabit ethernet 1) tsec1_col/ gpio2[20] m26 i/o ov dd tsec1_crs/ gpio2[21] u25 i/o lv dd1 tsec1_gtx_clk v24 o lv dd1 3 tsec1_rx_clk u26 i lv dd1 tsec1_rx_dv u24 i lv dd1 tsec1_rx_er/ gpio2[26] l28 i/o ov dd tsec1_rxd[7:4]/ gpio2[22:25] m27, m28, n26, n27 i/o ov dd tsec1_rxd[3:0] w26, w24, y28, y27 i lv dd1 tsec1_tx_clk n25 i ov dd tsec1_txd[7:4]/ gpio2[27:30] n28, p25, p26, p27 i/o ov dd tsec1_txd[3:0] v28, v27, v26, w28 o lv dd1 tsec1_tx_en w27 o lv dd1 tsec1_tx_er/ gpio2[31] n24 i/o ov dd three-speed ethernet contro ller (gigabit ethernet 2) tsec2_col/ gpio1[21] p28 i/o ov dd tsec2_crs/ gpio1[22] ac28 i/o lv dd2 tsec2_gtx_clk ac27 o lv dd2 tsec2_rx_clk ab25 i lv dd2 tsec2_rx_dv/ gpio1[23] ac26 i/o lv dd2 tsec2_rxd[7:4]/ gpio1[26:29] r28, t24, t25, t26 i/o ov dd table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 81 tsec2_rxd[3:0]/ gpio1[13:16] aa25, aa26, aa27, aa28 i/o lv dd2 tsec2_rx_er/ gpio1[25] r25 i/o ov dd tsec2_txd[7]/ gpio1[31] t27 i/o ov dd tsec2_txd[6]/ dr_xcvr_term_sel t28 o ov dd tsec2_txd[5]/ dr_utmi_opmode1 u28 o ov dd tsec2_txd[4]/ dr_utmi_opmode0 u27 o ov dd tsec2_txd[3:0]/ gpio1[17:20] ab26, ab27, aa24, ab28 i/o lv dd2 tsec2_tx_er/ gpio1[24] r27 i/o ov dd tsec2_tx_en/ gpio1[12] ad28 i/o lv dd2 3 tsec2_tx_clk/ gpio1[30] r26 i/o ov dd duart uart_sout[1:2]/ msrcid[0:1]/lsrcid[0:1] b4, a4 o ov dd uart_sin[1:2]/ msrcid[2:3]/lsrcid[2:3] d5, c5 i/o ov dd uart_cts [1]/ msrcid4/lsrcid4 b5 i/o ov dd uart_cts [2]/ mdval/ ldval a5 i/o ov dd uart_rts [1:2] d6, c6 o ov dd i 2 c interface iic1_sda e5 i/o ov dd 2 iic1_scl a6 i/o ov dd 2 iic2_sda b6 i/o ov dd 2 iic2_scl e7 i/o ov dd 2 spi spimosi d7 i/o ov dd spimiso c7 i/o ov dd spiclk b7 i/o ov dd spisel a7 i ov dd table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 82 freescale semiconductor clocks pci_clk_out[0:4] y1, w3, w2, w1, v3 o ov dd pci_sync_in/pci_clock u4 i ov dd pci_sync_out u5 o ov dd 3 rtc/pit_clock e9 i ov dd clkin w5 i ov dd jtag tck h27 i ov dd tdi h28 i ov dd 4 tdo m24 o ov dd 3 tms j27 i ov dd 4 trst k26 i ov dd 4 test test f28 i ov dd 6 test_sel t3 i ov dd 6 pmc quiesce k27 o ov dd system control poreset k28 i ov dd hreset m25 i/o ov dd 1 sreset l27 i/o ov dd 2 thermal management therm0 b15 i ?8 power and ground signals av dd 1 c15 power for e300 pll (1.2 v) av dd 1 av dd 2u1 power for system pll (1.2 v) av dd 2 av dd 3 af9 power for ddr dll (1.2 v) av dd 3 table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 83 av dd 4u2 power for lbiu dll (1.2 v) av dd 4 gnd a2, b1, b2, d10, d18, e6, e14, e22, f9, f12, f15, f18, f21, f24, g5, h6, j23, l4, l6, l12, l13, l14, l15, l16, l17, m11, m12, m13, m14, m15, m16, m17, m18, m23, n11, n12, n13, n14, n15, n16, n17, n18, p6, p11, p12, p13, p14, p15, p16, p17, p18, p24, r5, r11, r12, r1 3, r14, r15, r16, r17, r18, r23, t11, t12, t13, t14, t15, t16, t17, t18, u6, u11, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v23, v25, w4, y6, aa23, ab24, ac5, ac8, ac11, ac14, ac17, ac20, ad9, ad15, ad21, ae12, ae18, af 3, af26 ?? gv dd u9, v9, w10, w19, y11, y12, y14, y15, y17, y18, aa6, ab5, ac9, ac12, ac15, ac18, ac21, ac24, ad6, ad8, ad14, ad20, ae5, ae11, ae17, ag2, ag27 power for ddr dram i/o voltage (2.5 v) gv dd lv dd1 u20, w25 power for three speed ethernet #1 and for ethernet management interface i/o (2.5v, 3.3v) lv dd1 lv dd2 v20, y23 power for three speed ethernet #2 i/o (2.5v, 3.3v) lv dd2 v dd j11, j12, j15, k10, k11, k12, k13, k14, k15, k16, k17, k18, k19, l10, l11, l18, l19, m10, m19, n10, n19, p9, p10, p19, r10, r19, r20, t10, t19, u10, u19, v10, v11, v18, v19, w11, w12, w13, w14, w15, w16, w17, w18 power for core (1.2 v) v dd ov dd b27, d3, d11, d19, e1 5, e23, f5, f8, f11, f14, f17, f20, g24, h2 3, h24, j6, j14, j17, j18, k4, l9, l20, l23, l25, m6, m9, m20, p5, p20, p23, r6, r9, r24, u23, v4, v6 pci, 10/100 ethernet, and other standard (3.3 v) ov dd mvref1 af19 i ddr reference voltage mvref2 ae10 i ddr reference voltage table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 84 freescale semiconductor pins reserved for future ddr2 (they should be left unconnected for 8347) odt[0:3] ag5, ad4, ah6, af4 ? ? mba[2] ad22 no connection nc v1, v2, v5 spare1 af12 ? ? 7 spare2 ag11 ? ? 6 notes: 1. this pin is an open drain signal. a weak pull-up resistor (1 k ? ) should be placed on this pin to ov dd 2. this pin is an open drain signal. a weak pull-up resistor (2?10 k ? ) should be placed on this pin to ov dd . 3. this output is actively driven during reset rather than being three-stated during reset. 4. these jtag pins have weak internal pull-up p-fets that are always enabled. 5. this pin should have a weak pull up if the chip is in pci host mode. follow pci specifications recommendation. 6. .this pin must always be tied to gnd 7. this pin must always be left not connected 8. thermal sensitive resistor. table 49. mpc8347e (pbga) pinout listing (continued) signal package pin number pin type power supply notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 85 clocking 18 clocking figure 38 shows the internal distribution of clocks within the mpc8347e. figure 38. mpc8347e clock subsystem the primary clock source for the mpc8347e can be one of two input s, clkin or pci_clk, depending on whether the device is configured in pci host or pci agent mode. when the mpc8347e is configured as a pci host device, clkin is its primary i nput clock. clkin feeds th e pci clock divider ( 2) and the multiplexors for pci_sync_out and pci_clk_ out. the cfg_clkin_div configuration input selects whether clkin or clkin/ 2 is driven out on the pci_sy nc_out signal. the occr[pcicd n ] parameters select whether clkin or clki n/2 is driven out on the pci_clk_out n signals. pci_sync_out is connected externally to pci_sy nc_in to allow the internal clock subsystem to synchronize to the system pci clocks. pci_sync_out must be connected properly to pci_sync_in, with equal delay to all pci agent devices in the system, to allow the mpc8347e to function. when the mpc8347e is configured as a pc i agent device, pci_clk is the primary input clock. when the mpc8347e is configured as a pci agent devi ce the clkin signal should be tied to gnd. core pll system pll ddr lbiu lsync_in lsync_out lclk[0:2] mck[0:5] mck [0:5] core_clk e300 core csb_clk to rest clkin csb_clk mpc8347e 6 6 ddr memory local bus pci_clk_out[0:4] pci_sync_out pci_clk/ clock unit of the device ddr_clk lbiu_clk cfg_clkin_div pci clock pci_sync_in device memory device /n to local bus memory controller to ddr memory controller dll clock div /2 divider 5
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 86 freescale semiconductor clocking as shown in figure 38 , the primary clock input (frequency) is multiplied up by the system phase-locked loop (pll) and the clock unit to create the cohere nt system bus clock ( csb_clk ), the internal clock for the ddr controller ( ddr_clk ), and the internal clock for the local bus interface unit ( lbiu_clk ). the csb_clk frequency is derived from a co mplex set of factors that can be simplified into the following equation: csb_clk = {pci_sync_in (1 + cfg_clkin_div)} spmf in pci host mode, pci_sync_in (1 + cf g_clkin_div) is the clkin frequency. the csb_clk serves as the clock input to the e300 core. a second pll inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core ( core_clk ). the system and core pll multipliers are selected by the spmf and corepll fi elds in the reset confi guration word low (rcwl) which is loaded at power-on reset or by one of the hard-coded reset options. see chapter 4, ?reset, clocking, and initia lization,? in the mpc8349e reference manual for more information on the clock subsystem. the internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk (1 + rcwl[ddrcm] note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the ddr clock divider ( 2) to create the differential ddr me mory bus clock outputs (mck and mck ). however, the data rate is the same frequency as ddr_clk . the internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk (1 + rcwl[lbiucm] note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the a lbiu clock divider to create the external local bus clock outputs (l sync_out and lclk[0:2]). the lbiu clock divider ratio is controlled by lccr[clkdiv]. in addition, some of the internal uni ts may be required to be shut off or operate at lower frequency than the csb_clk frequency. those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. table 50 specifies which units have a configurable clock frequency. table 50. configurable clock units unit default frequency options tsec2, i 2 c1 csb_clk /3 off, csb_clk , csb_clk /2, csb_clk /3 security core csb_clk /3 off, csb_clk , csb_clk/2, csb_clk /3 pci and dma complex csb_clk off, csb_clk
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 87 clocking table 51 provides the operating frequencies for th e mpc8347e tbga under recommended operating conditions (see table 64 ). table 52 provides the operating frequencies for th e mpc8347e pbga under recommended operating conditions (see). table 51. operating frequencies for tbga characteristic 1 1 the clkin frequency, rcwl[spmf], a nd rcwl[corepll] settings must be chosen such that the resulting ccb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. the value of sccr[enccm], sccr[us bdrcm]and sccr[usbmphcm] must be programmed such that the maximum internal operating frequency of the security core and usb modules will not exceed their respective value listed in this table. 533 mhz 667 mhz unit e300 core frequency ( core_clk ) tbd-533 tbd-667 mhz coherent system bus frequency ( csb_clk ) 100?266 100?300 mhz ddr memory bus frequency (mclk) 2 2 the ddr data rate is 2x the ddr memory bus frequency. 100-133 100-166.67 mhz local bus frequency (lclk n ) 3 3 the local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on lccr[clkdiv]) which is in turn 1x or 2x the ccb_clk frequency (depending on rcwl[lbiucm]). 16.67-133 16.67-133 mhz pci input frequency (clkin or pci_clk) 25-66 25-66 mhz security core maximum internal operating frequency 133 166 mhz usb_dr, usb_mph maximum internal operating frequency 133 166 mhz table 52. operating frequencies for pbga characteristic 1 266 mhz 333 mhz 400 mhz unit e300 core frequency ( core_clk ) tbd-266 tbd-333 tbd-400 mhz coherent system bus frequency ( csb_clk ) 100?333 mhz ddr memory bus frequency (mclk) 2 100-166.67 mhz local bus frequency (lclk n ) 3 16.67-133 mhz pci input frequency (clkin or pci_clk) 25-66 mhz
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 88 freescale semiconductor clocking 18.1 system pll configuration the system pll is controlled by the rcwl[spmf] parameter. table 53 shows the multiplication factor encodings for the system pll. security core maximum internal operating frequency 133 mhz usb_dr, usb_mph maximum internal operating frequency 133 mhz 1 the clkin frequency, rcwl[spmf], and rcwl[corepl l] settings must be chosen such that the resulting ccb_clk , mclk, lclk[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. the value of sccr[enccm], sccr[usbdrcm]and sccr[usbmphcm] must be programmed such that t he maximum internal operating frequency of the security core and usb modules will not exceed their respective value listed in this table. 2 the ddr data rate is 2x the ddr memory bus frequency. 3 the local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on lccr[clkdiv]) which is in turn 1x or 2x the ccb_clk frequency (depending on rcwl[lbiucm]). table 53. system pll multiplication factors rcwl[spmf] system pll multiplication factor 0000 16 0001 reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 table 52. operating frequencies for pbga (continued) characteristic 1 266 mhz 333 mhz 400 mhz unit
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 89 clocking as described in section 18, ?clocking ,? the lbiucm, ddrcm, and spm f parameters in the reset configuration word low and the cf g_clkin_div configuration input si gnal select the ratio between the primary clock input (clkin or pci_clk) and the internal coherent system bus clock ( csb_clk ). table 54 and table 55 shows the expected frequency values for the csb frequency for select csb_clk to clkin/pci_sync_in ratios. table 54. csb frequency options for host mode cfg_clkin_div at reset 1 1 cfg_clkin_div select the rati o between clkin and pci_sync_out. spmf csb_clk : input clock ratio 2 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz) low 0010 2 : 1 133 low 0011 3 : 1 100 200 low 0100 4 : 1 100 133 266 low 0101 5 : 1 125 166 333 low 0110 6 : 1 100 150 200 low 0111 7 : 1 116 175 233 low 1000 8 : 1 133 200 266 low 1001 9 : 1 150 225 300 low 1010 10 : 1 166 250 333 low 1011 11 : 1 183 275 low 1100 12 : 1 200 300 low 1101 13 : 1 216 325 low 1110 14 : 1 233 low 1111 15 : 1 250 low 0000 16 : 1 266 high 0010 2 : 1 133 high 0011 3 : 1 100 200 high 0100 4 : 1 133 266 high 0101 5 : 1 166 333 high 0110 6 : 1 200 high 0111 7 : 1 233 high 1000 8 : 1
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 90 freescale semiconductor clocking 18.2 core pll configuration rcwl[corepll] selects the ratio between th e internal coherent system bus clock ( csb_clk ) and the e300 core clock ( core_clk ). table 56 shows the encodings for rcwl[cor epll]. corepll values that are not listed in table 56 should be considered as reserved. table 55. csb frequency options for agent mode cfg_clkin_div at reset 1 1 cfg_clkin_div doubles csb_clk if set high. spmf csb_clk : input clock ratio 2 2 clkin is the input clock in host mode; pci_clk is the input clock in agent mode. input clock frequency (mhz) 2 16.67 25 33.33 66.67 csb_clk frequency (mhz) low 0010 2 : 1 133 low 0011 3 : 1 100 200 low 0100 4 : 1 100 133 266 low 0101 5 : 1 125 166 333 low 0110 6 : 1 100 150 200 low 0111 7 : 1 116 175 233 low 1000 8 : 1 133 200 266 low 1001 9 : 1 150 225 300 low 1010 10 : 1 166 250 333 low 1011 11 : 1 183 275 low 1100 12 : 1 200 300 low 1101 13 : 1 216 325 low 1110 14 : 1 233 low 1111 15 : 1 250 low 0000 16 : 1 266 high 0010 4 : 1 100 133 266 high 0011 6 : 1 100 150 200 high 0100 8 : 1 133 200 266 high 0101 10 : 1 166 250 333 high 0110 12 : 1 200 300 high 0111 14 : 1 233 high 1000 16 : 1 266
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 91 clocking note core vco frequency = core frequency vco divider vco divider has to be set properly so th at the core vco frequency is in the range of 800?1800 mhz. table 56. e300 core pll configuration rcwl[corepll] core_clk : csb_clk ratio vco divider 1 1 core vco frequency = core frequency vco divider. note that vco divider has to be set properly so that the core vco frequency is in the range of 800?1800 mhz. 0-1 2-5 6 nn 0000 n pll bypassed (pll off, csb_clk clocks core directly) pll bypassed (pll off, csb_clk clocks core directly) 00 0001 01:1 2 01 0001 01:1 4 10 0001 01:1 8 11 0001 01:1 8 00 0001 1 1.5:1 2 01 0001 1 1.5:1 4 10 0001 1 1.5:1 8 11 0001 1 1.5:1 8 00 0010 02:1 2 01 0010 02:1 4 10 0010 02:1 8 11 0010 02:1 8 00 0010 1 2.5:1 2 01 0010 1 2.5:1 4 10 0010 1 2.5:1 8 11 0010 1 2.5:1 8 00 0011 03:1 2 01 0011 03:1 4 10 0011 03:1 8 11 0011 03:1 8
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 92 freescale semiconductor clocking 18.3 suggested pll configurations table 57 shows suggested pll configurations for 33 mhz and 66 mhz input clocks. table 57. suggested pll configurations ref no. 1 rcwl 400 mhz device 533 mhz device 667 mhz device spmf core pll input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) 33 mhz clkin/pci_clk options 902 1001 0000010 33 300 300 33 300 (tbd) 30033300300 922 1001 0100010 33 300 300 33 300 (tbd) 30033300300 703 0111 0000011 33 233 350 33 233 350 33 233 350 723 0111 0100011 33 233 350 33 233 350 33 233 350 604 0110 0000100 33 200 400 33 200 400 33 200 400 624 0110 0100100 33 200 400 33 200 400 33 200 400 803 1000 0000011 33 266 400 33 266 400 33 266 400 823 1000 0100011 33 266 400 33 266 400 33 266 400 903 1001 0000011 ?33300 (tbd) 45033300450 923 1001 0100011 ?33300 (tbd) 45033300450 704 0111 0000011 ? 3323346633233466 724 0111 0100011 ? 3323346633233466 804 1000 0000100 ? 3326653333266533 705 0111 0000101 ? ? 33 233 583 606 0110 0000110 ? ? 33 200 600 904 1001 0000100 ? ? 33 300 600 805 1000 0000101 ? ? 33 266 667 a04 1010 0000100 ? ? 33 333 667 66 mhz clkin/pci_clk options 304 0011 0000100 66 200 400 66 200 400 66 200 400 324 0011 0100100 66 200 400 66 200 400 66 200 400 403 0100 0000011 66 266 400 66 266 400 66 266 400
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 93 clocking 423 0100 0100011 66 266 400 66 266 400 66 266 400 305 0011 0000101 ? 6620050066200500 404 0100 0000100 ? 6626653366266533 306 0011 0000100 ? ? 66 200 600 405 0100 0000101 ? ? 66 266 667 504 0101 0000100 ? ? 66 333 667 1 the pll configuration reference number is the hexadecimal representation of rcwl, bits 4-15 associated with the spmf and corepll settings given in the table. 2 the input clock is clkin for pci host mode or pci_clk for pci agent mode. table 57. suggested pll configurations (continued) ref no. 1 rcwl 400 mhz device 533 mhz device 667 mhz device spmf core pll input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz) input clock freq (mhz) 2 csb freq (mhz) core freq (mhz)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 94 freescale semiconductor thermal 19 thermal this section describes the therma l specifications of the mpc8347e. 19.1 thermal characteristics table 58 provides the package therma l characteristics for the 672 35x35 mm tbga of the mpc8347e. table 59 provides the package therma l characteristics for the 620 29x29 mm pbga of the mpc8347e. table 58. package thermal characteristics for tbga characteristic symbol value unit notes junction-to-ambient natural convection on single-layer board (1s) r ja 14 c/w 1, 2 junction-to-ambient natural convection on four-layer board (2s2p) r jma 11 c/w 1, 3 junction-to-ambient (@200 ft/min) on single-layer board (1s) r jma 11 c/w 1, 3 junction-to-ambient (@ 200 ft/min) on four-layer board (2s2p) r jma 8c/w1, 3 junction-to-ambient (@ 2 m/s) on single-layer board (1s) r jma 9c/w1, 3 junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) r jma 7c/w1, 3 junction-to-board thermal r jb 3.8 c/w 4 junction-to-case thermal r jc 1.7 c/w 5 junction-to-package natural convection on top jt 1c/w6 notes 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, powe r dissipation of other compon ents on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (lfm). 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as m easured by the cold pl ate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 59. package thermal characteristics for pbga characteristic symbol value unit notes junction-to-ambient natural convection on single layer board (1s) r ja 21 c/w 1, 2 junction-to-ambient natural convection on four layer board (2s2p) r jma 15 c/w 1, 3 junction-to-ambient (@200 ft/min) on single layer board (1s) r jma 17 c/w 1, 3
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 95 thermal 19.2 thermal management information for the following sections, p d = (v dd x i dd ) + p i/o where p i/o is the power dissipation of the i/o drivers. 19.2.1 estimation of junction temp erature with junction-to-ambient thermal resistance an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + ( r ja p d ) where: t a = ambient temperature for the package ( c) r ja = junction to ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an i ndustry standard value that provides a quick and easy estimation of thermal performance. as a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed circuit boar d. the value obtained on the board with the internal planes is usually appropriate if th e board has low power diss ipation and the component s are well separated. test cases have demonstrated that errors of a factor of two (in the quantity t j - t a ) are possible. junction-to-ambient (@ 200 ft/min) on four layer board (2s2p) r jma 12 c/w 1, 3 junction-to-board thermal r jb 6c/w4 junction-to-case thermal r jc 5c/w5 junction-to-package natural convection on top jt 5c/w6 notes 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, powe r dissipation of other compon ents on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as m easured by the cold pl ate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. table 59. package thermal characteristics for pbga (continued) characteristic symbol value unit notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 96 freescale semiconductor thermal 19.2.2 estimation of junction te mperature with junction-to-board thermal resistance the thermal performance of a device cannot be adequa tely predicted from the j unction to ambient thermal resistance. the thermal performan ce of any component is strongly de pendent on the power dissipation of surrounding components. in addition, the ambient temperature varies wi dely within the application. for many natural convection and especial ly closed box applications, the boa rd temperature at the perimeter (edge) of the package will be approximately the sa me as the local air temperature near the device. specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions th at determine the temperature of the device. at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t a + ( r ja p d ) where: t a = ambient temperature for the package ( c) r ja = junction to ambient thermal resistance ( c/w) p d = power dissipation in the package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the appli cation board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 19.2.3 experimental determinat ion of junction temperature to determine the junction temperatur e of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: t t = thermocouple temperature on top of package ( c) jt = junction to ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the thermal characterization parame ter is measured per jesd51-2 spec ification using a 40 gauge type t thermocouple epoxied to the top center of the pack age case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 97 thermal 19.2.4 heat sinks and juncti on-to-case thermal resistance in some application envi ronments, a heat sink will be required to provide the necessary thermal management of the device. when a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ja = r jc + r ca where: r ja = junction to ambient thermal resistance ( c/w) r jc = junction to case th ermal resistance ( c/w) r ca = case to ambient thermal resistance ( c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the user can ch ange the size of the heat sink, the air flow around the device, the interface material, the mounti ng arrangement on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. the heat sink choice is determined by the application environment (temperature, air flow, ad jacent component power dissipation) and the physical space available. because there is not a standard appl ication environment, a standard heat sink is not required. table 60 and table 61 show heat sinks and junction-to-case th ermal resistance for tbga and pbga of the mpc8347e.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 98 freescale semiconductor thermal table 60. heat sinks and junction-to-case thermal resistance of mpc8347e (tbga) heat sink assuming thermal grease air flow 35x35 mm tbga junction-to-ambient thermal resistance aavid 30x30x9.4 mm pin fin natural convention 10 aavid 30x30x9.4 mm pin fin 1 m/s 6.5 aavid 30x30x9.4 mm pin fin 2 m/s 5.6 aavid 31x35x23 mm pin fin natural convention 8.4 aavid 31x35x23 mm pin fin 1 m/s 4.7 aavid 31x35x23 mm pin fin 2 m/s 4 wakefield, 53x53x25 mm pin fin natural convention 5.7 wakefield, 53x53x25 mm pin fin 1 m/s 3.5 wakefield, 53x53x25 mm pin fin 2 m/s 2.7 mei, 75x85x12 no adjacent board, extrusion natural convention 6.7 mei, 75x85x12 no adjacent board, extrusion 1 m/s 4.1 mei, 75x85x12 no adjacent board, extrusion 2 m/s 2.8 mei, 75x85x12 mm, adjacent board, 40 mm side bypass 1 m/s 3.1 table 61. heat sinks and junction-to-case thermal resistance mpc8347e(pbga) heat sink assuming thermal grease air flow 29x29 mm pbga junction-to-ambient thermal resistance aavid 30x30x9.4 mm pin fin natural convention 13.5 aavid 30x30x9.4 mm pin fin 1 m/s 9.6 aavid 30x30x9.4 mm pin fin 2 m/s 8.8 aavid 31x35x23 mm pin fin natural convention 11.3 aavid 31x35x23 mm pin fin 1 m/s 8.1 aavid 31x35x23 mm pin fin 2 m/s 7.5 wakefield, 53x53x25 mm pin fin natural convention 9.1 wakefield, 53x53x25 mm pin fin 1 m/s 7.1 wakefield, 53x53x25 mm pin fin 2 m/s 6.5 mei, 75x85x12 no adjacent board, extrusion natural convention 10.1 mei, 75x85x12 no adjacent board, extrusion 1 m/s 7.7 mei, 75x85x12 no adjacent board, extrusion 2 m/s 6.6 mei, 75x85x12 mm, adjacent board, 40 mm side bypass 1 m/s 6.9
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 99 thermal accurate thermal design requires thermal modeling of the application environm ent using computational fluid dynamics software which can model both the conduction cooling a nd the convection cooling of the air moving through the application. si mplified thermal models of the pa ckages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in th e thermal resistance table. more detailed thermal models can be made available on request. heat sink vendors incl ude the following list: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aav idthermalloy.com alpha novatech 408-567-8082 473 sapena ct. #12 santa clara, ca 95054 internet: www.alp hanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com tyco electronics 800-522-2800 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com interface material vendors include the following: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 100 freescale semiconductor thermal dow-corning corporation 800-248-2481 dow-corning electronic materials p.o. box 994 midland, mi 48686-0997 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 19.3 heat sink attachment when attaching heat sinks to these devices, an inte rface material is required. the best method is to use thermal grease and a spring clip. the spring clip shoul d connect to the printed ci rcuit board, either to the board itself, to hooks soldered to th e board, or to a plastic stiffener. avoid attachment fo rces which would lift the edge of the package or peel the package from the board. such peeling forc es reduce the solder joint lifetime of the package. recomm ended maximum force on the top of the package is 10 lb force (4.5 kg force). if an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance ve rified under the application requirements. 19.3.1 experimental determination of the junction temperature with a heat sink when heat sink is used, the juncti on temperature is determined from a thermocouple inserted at the interface between the case of the package and the in terface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many e ngineers measure the heat sink temperature and then back calculate the case temperature using a separa te measurement of the thermal resistance of the interface. from this case temperat ure, the junction temperature is de termined from the junction to case thermal resistance. t j = t c + ( r ja p d ) where: t c = case temperature of the package ( c) r jc = junction to case th ermal resistance ( c/w) p d = power dissipation (w)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 101 system design information 20 system design information this section provides elect rical and thermal design r ecommendations for successf ul application of the mpc8347e. 20.1 system clocking the mpc8347e includes two plls. 1. the platform pll (av dd 1 ) generates the platform clock from the externally supplied clkin input. the frequency ratio between the platform and clkin is selected using the platform pll ratio configuration bits as described in section 18.1, ?system pll configuration .? 2. the e300 core pll (av dd 2 ) generates the core clock as a slave to the platform clock. the frequency ratio between the e300 core clock and the platform cl ock is selected using the e300 pll ratio configuration bits as described in section , ? .? 20.2 pll power supply filtering each of the plls listed above is provided wi th power through indepe ndent power supply pins (av dd 1,av dd 2 respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be deri ved directly from v dd through a low frequency filter sc heme such as the following. there are a number of ways to relia bly provide power to the plls, but the recommended solution is to provide five independe nt filter circuits as illustrated in figure 39 , one to each of the five av dd pins. by providing independent filters to eac h pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommenda tions of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route direct ly from the capacitors to the av dd pin, which is on the periphery of pack age, without the inductance of vias. figure 39 shows the pll power supply filter circuit. figure 39. pll power supply filter circuit v dd av dd (or l2av dd ) 2.2 f 2.2 f gnd low esl surface mount capacitors 10 ?
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 102 freescale semiconductor system design information 20.3 decoupling recommendations due to large address and da ta buses, and high operati ng frequencies, the mpc8347e can generate transient power surges and high freque ncy noise in its power suppl y, especially while drivi ng large capacitive loads. this noise must be prevented from reaching ot her components in the mpc8347e system, and the mpc8347e itself requires a clean, tight ly regulated source of power. ther efore, it is recommended that the system designer place at least one decoupli ng capacitor at each v dd , ov dd , gv dd , and lv dd pins of the mpc8347e. these decoupling capacitors s hould receive their power from separate v dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, util izing short traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a va lue of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be severa l bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors shoul d have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connect ed to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 20.4 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , gv dd , or lv dd as required. unused active high inputs should be connected to gnd. all nc ( no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , lv dd , ov dd , and gnd pins of the mpc8347e. 20.5 output buffer dc impedance the mpc8347e drivers are characterize d over process, voltage, and temper ature. for all buses, the driver is a push-pull single-ended driv er type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external re sistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until th e pad voltage is ov dd /2 (see figure 40 ). the output impedance is the av erage of two components, the resistances of the pul l-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistan ce of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2.
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 103 system design information figure 40. driver impedance measurement the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the out put voltage is measured while driving l ogic 1 without an exte rnal differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precisi on differential termination resistor of value r term . the measured voltage is v 2 = 1/(1/r 1 +1/r 2 )) i source . solving for the outpu t impedance gives r source = r term (v 1 /v 2 ? 1). the drive current is then i source =v 1 /r source . table 62 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. 20.6 configuration pin muxing the mpc8347e provides the user with power-on confi guration options which can be set through the use of external pull-up or pul l-down resistors of 4.7 k ? on certain output pins (see customer visible configuration pins). these pins are generall y used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time th e input receiver is disabled and the i/o circuit takes on its nor mal function. careful board layout w ith stubless connections to these table 62. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci signals (not including pci output clocks) pci output clocks (including pci_sync_out) ddr dram symbol unit r n 42 target 25 target 42 target 20 target z 0 ? r p 42 target 25 target 42 target 20 target z 0 ? differential na na na na z diff ? note: nominal supply voltages. see ta b l e 6 3 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 104 freescale semiconductor system design information pull-up/pull-down resistors coupled wi th the large value of the pull-up/ pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. 20.7 pull-up resistor requirements the mpc8347e requires high resi stance pull-up resistors (10 k ? is recommended) on open drain type pins including i 2 c pins, ethernet management mdio pin and epic interrupt pins. correct operation of the jtag interface requires conf iguration of a group of system control pins as demonstrated in figure 41 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavi or and spurious assertion will give unpredictable results. refer to the pci 2.2 specification for all pull-ups required for pci. 20.8 jtag configuration signals boundary scan testing is enabled thro ugh the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provi ded on all processors that implem ent the powerpc architecture. the mpc8347e requires trst to be asserted during re set conditions to ensure the jtag boundary logic does not interfere with normal chip operati on. while it is possible to force the tap controller to the reset state using only the tck and tms signals, ge nerally systems will assert trst during power-on reset. because the jtag interface is also used for accessing the common on-chip pro cessor (cop) function, simply tying trst to poreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging softwa re) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires th e ability to independently assert trst without causing poreset . if the target system has independent reset sources, such as voltage monito rs, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 41 allows the cop to independently assert hreset or trst , while ensuring that the targ et can drive hreset as well. if the jtag interface and cop header wi ll not be used, trst should be tied to poreset so that it is asserted when the system reset signal (poreset ) is asserted. the cop header shown figure 41 in adds many benefits?breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are po ssible through this interface?and can be as inexpensive as an unpopulated footpr int for a header to be added when needed. the cop interface has a standard header for conn ection to the target system, based on the 0.025" square-post, 0.100" centered header asse mbly (often called a berg header). there is no standardized way to number the cop header shown in figure 41 ; consequently, many different pin numbers have been observed from emulator vendors. some ar e numbered top-to-bottom then left-to-right, while others use left-t o-right then top-to-bottom, while st ill others number the pins counter
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 105 system design information clockwise from pin 1 (as with an ic). regardless of the numberi ng, the signal placement recommended in figure 41 is common to all known emulators. figure 41. jtag interface connection hreset hreset from target board sources hreset 13 sreset sreset sreset nc nc 11 vdd_sense 6 1 5 15 2 k ? 10 k ? 10 k ? ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 2 notes: 2. key location; pin 14 is not physically present on the cop header. ov dd ov dd 10 k ? ov dd trst 10 k ? ov dd 10 k ? 10 k ? chkstp_out chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pin out 1 2 nc poreset poreset 1. some systems require power to be fed from the application board in to the debugger repeater card via the cop header. in this case the resistor value for vdd_sense should be around 20 ? . nc
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 106 freescale semiconductor electrical characteristics 21 electrical characteristics this section provides the ac and dc electrical specifications and th ermal charaistics for the mpc8347e. the mpc8347e is currently targeted to these specifications. some of th ese specifications are independent of the i/o cell, but are included for a more comple te reference. these are not purely i/o buffer design specifications. 21.1 overall dc electrical characteristics this section covers the ratings, c onditions, and other characteristics. 21.1.1 absolute maximum ratings table 63 provides the absolute maximum ratings. table 63. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage v dd ?0.3 to 1.32 v pll supply voltage av dd ?0.3 to 1.32 v ddr dram i/o voltage gv dd ?0.3 to 3.63 v three-speed ethernet i/o, mii management voltage lv dd ?0.3 to 3.63 v pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v input voltage ddr dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 5 ddr dram reference mv ref ?0.3 to (gv dd + 0.3) v 2, 5 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v 4, 5 local bus, duart, clkin, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 3, 5 pci ov in ?0.3 to (ov dd + 0.3) v 6
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 107 electrical characteristics 21.1.2 power supply voltage specification table 64 provides the recommended opera ting conditions for the mpc8347e. note that the values in table 64 are the recommended and tested operating conditions. proper devi ce operation outside of these conditions is not guaranteed. storage temperature range t stg ?55 to 150 c notes: 1. functional and tested operating conditions are given in ta bl e 6 4 . absolute maximum rating s are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit ma y be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: lv in must not exceed lv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 42 . 6. ov in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 3. table 64. recommended operating conditions characteristic symbol recommended value unit notes core supply voltage v dd 1.2 v 60 mv v 1 pll supply voltage av dd 1.2 v 60 mv v 1 ddr dram i/o supply voltage gv dd 2.5 v 125 mv v three-speed ethernet i/o supply voltage lv dd1 3.3 v 330 mv 2.5 v 125 mv v three-speed ethernet i/o supply voltage lv dd2 3.3 v 330 mv 2.5 v 125 mv v pci, local bus, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 330 mv v notes: 1. gvdd, lvdd, ovdd, avdd, and vdd must track each other and must vary in the same direction?either in the positive or negative direction. table 63. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 108 freescale semiconductor electrical characteristics figure 42 shows the undershoot and overshoot voltages at the in terfaces of the mpc8347e. figure 42. overshoot/undershoot voltage for gv dd /ov dd /lv dd figure 43 shows the undershoot and overshoot voltage of the pci interfac e of the mpc8347e for the 3.3-v signals, respectively. figure 43. maximum ac waveforms on pci interface for 3.3-v signaling gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/ov dd + 20% g/l/ov dd g/l/ov dd + 5% of t interface 1 1. note that t interface refers to the clock period associ ated with the bu s clock interface. v ih v il note: undervoltage waveform overvoltage waveform 11 ns (min) +7.1 v 7.1 v p-to-p (min) 4 ns (max) ?3.5 v 7.1 v p-to-p (min) 62.5 ns +3.6 v 0 v 4 ns (max)
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 109 electrical characteristics 21.1.3 output driver characteristics table 65 provides information on the characteristics of the output driver stre ngths. the values are preliminary estimates. 21.2 power sequencing mpc8347e does not require the core supply voltage and io supply voltages to be a pplied in any particular order. note that during the power ramp up, before th e power supplies are stable, there might be a period of time that io pins are ac tively driven. after the power is stable, as long as poreset is asserted, most io pins are tri-stated. in order to minimize the time th at io pins being actively driven, it is recommended to apply core voltage before io voltage and assert poreset before the power supplies fully ramp up. table 65. output drive capability driver type output impedance ( ? ) supply voltage local bus interface utilities signals 42 ov dd = 3.3 v pci signals (not including pci output clocks) 25 pci output clocks (including pci_sync_out) 42 ddr signal 20 gv dd = 2.5 v tsec/10/100 signals 42 lv dd = 2.5/3.3 v duart, system control, i2c, jtag 42 ov dd = 3.3 v gpio signals 42 ov dd = 3.3 v, lv dd = 2.5/3.3 v
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 110 freescale semiconductor document revision history 22 document revision history table 66 provides a revision history of this document. 23 ordering information ordering information for the part s fully covered by this specifi cation document is provided in section 23.1, ?part numbers fully addressed by this document .? 23.1 part numbers fully addressed by this document table 67 provides the freescale part num bering nomenclature for the mpc 8347e. note that the individual part numbers correspond to a maximum processor core frequency. for av ailable frequencies, contact your local freescale sales office. in a ddition to the processor frequency, the part numbering scheme also includes an application modifier wh ich may specify special application conditions. each part number also contains a revision code which refe rs to the die mask revision number. table 66. document revision history revision date substantive change(s) 5 10/2005 in ta b l e 6 0 , updated aavid 30x30x9.4 mm pin fin (natural convection) junction-to-ambient thermal resistance, from 11 to 10. changed classification of document to ?technical data.? 4 9/2005 added ta b l e 2 , "mpc8347e typical i/o power dissipation." 3 8/2005 ta bl e 1 : updated values for power dissipation that were tbd in revision 2. 2 5/2005 ta bl e 1 : typical values for power dissipation are changed to "tbd". ta bl e 4 8 : foot note numbering was wrong. therm0 should have foot note "9" instead of "8". 1 4/2005 ta bl e 1 : addition of note 1 ta bl e 4 8 : addition of therm0 (k32) ta bl e 4 9 : addition of therm0 (b15) 0 4/2005 ?
mpc8347e powerquicc ii pro integrated host processor hardware specifications, rev. 5 freescale semiconductor 111 ordering information table 67. part numbering nomenclature mpc nnnn et pp aa a r product code part identifier encryption acceleration temperature 1 range package 2 processor frequency 3 platform frequency revision level mpc 8347 blank = not included e = included blank = 0 to 105 c c= -40 to 105 c zu =tbga vv = pb free tbga zq = pbga vr = pb free pbga e300 core speed ad =266 ag = 400 aj = 533 al = 667 d = 266 f = 333 contact local freescale sales office notes: 1. for temperature range = c, processor frequency is limited to "tbd" with a platform frequency of "tbd". 2. see section 1.13, ?package and pin listings? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, part s addressed by part number specifications may support other maximum core frequencies.
document number: mpc8347eec rev. 5 10/2005 freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2005. information in this document is provid ed solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental da mages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or spec ifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 2666 8080 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 (800) 441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com this page intentionally left blank
part numbe r contains go keyword search go advanced | parametric home | contact us products applications technologies support where to buy about freescale freescale > powerquicc communications processors > mpc83xx powerquicc ii pro processors > mpc8347e mpc8347e : powerquicc ii pro famil y subscribe the mpc8349e powerquicc ii? pro family of integrated communications processors is a next-generation extension of the p opular powerquicc ii line. based on a system-on-chip (soc) architecture, the mpc8349e powerquicc ii pro family integrates the enhanced e300 powerpc? core and advanced features, such as ddr memory, du al gigabit ethernet, dual pci and hi-speed usb controllers. with clock speeds scaling to 667 mhz, the mpc8349e family of processors offers the highest p erforming powerquicc ii devices available. the mpc8349e powerquicc ii pro family is designed to p rovide a cost-effective, highly integrated control processing solution that addresses the emerging needs of networking, communications and pervasive computing applications. mpc8349e processors can be used in applications such as ethernet routers and switches, wireless lan (wlan) equipment, network storage, home network appliances, industrial control equipment, and copiers, printers and other imaging systems. e300 soc platform the mpc8349e powerqui cc ii pro family is based on the e300 soc platform?making it easy and fast to add or remove functional blocks and devel op additional soc-based family members targeting emerging market requirements. at the heart of the e300 soc platform is freescale semiconductor's e300 powerpc core. based on the cl assic powerpc instruction-set rate this page -- n m l k j - n m l k j 0 n m l k j + n m l k j ++ n m l k j submit care to comment? freescale semiconductor re g iste r lo g in basket pa g e 1 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
architecture, the e300 core is an enhanced version of the 603e powerpc core used in previ ous-generation powerquicc ii p rocessors. enhancements include twice as much l1 cache (32 kb data cache and 32 kb instruction cache) with integrated parity checking, and other performance-enhancing features. the e300 core is completely software-com patible with existing 603e core- based products. integrated security the mpc8349e family features a powerful integrated security engine derived from freescale semiconductor's security coprocessor product line. the mpc 8349e family's security engine supports des, 3des, md-5, sh a-1, aes, and arc-4 encryption algorithms, as well as a public key accelerator and an on-chip random number generator. the secu rity engine is capable of single-pass encryption and authen tication, as required by ipsec, ieee? 802.11i standard and ot her security protocols. product picture mpc8347e features e300 powerpc core operating from 400 mhz up to 667 mhz (enhanced version of 603e core with larger caches) z 32-bit, high-performan ce superscalar core z 1260 mips @ 667 mhz z double-precision floating point, in teger, load/store, system register, and branch processor units z 32 kb data and 32 kb instruction cache with line locking support z ddr memory controller, up to 333 mhz data rate, with 32- or 64-bit interfaces with ecc z dual pci interfaces z dual 10/100/1000 ethernet controllers link pa g e 2 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
z embedded security engine z dual hi-speed usb controllers z local bus controller z dual uart (duart) z dual i 2 c interfaces (maste r or slave mode) z four-channel dma controller z serial peripheral interface (spi) z general-purpose parallel i/o (gpio) z ieee 1149.1 jtag test access port z package: 672-pin, 35 mm x 35 mm tbga (1 mm pitch) z process technology: 130 nm cmos z voltage: 1.2v core voltage with 3.3v and 2.5v i/o return to to p mpc8347e parametrics package description pbga 620 29*29*1.2p1.0, tbga 672 35*35*1.5p1.0 view expanded set of parameters parametric search return to to p mpc8347e documentation documentation application notes pa g e 3 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
id and description vendor id format loading... an2582 hardware and layout design considera tions for ddr memory interfaces freescale pdf an2755 an2755: sec 2.0 descriptor programmer's guide freescale pdf an2810.pdf powerquicc upm configuration freescale pdf an2810sw.zip an2810 supporting files freescale zip an2583 programming the powerquicc ii i ddr sdram controller freescale pdf an2745 setting up tsec hash tables freescale pdf an2491 simplified mnemonics for powerpc instructions freescale pdf an2540 synchronizing instructions for powerp c(tm) instruction set architecture freescale pdf an2129 instruction and data cache locking on the g2 processor core freescale pdf data sheets id and description vendor id format mpc8347eec mpc8347e powerquicc ii pro integr ated host processor hardware specifications freescale pdf errata - click here for important errata information id and description vendor id format mpc8349ece mpc8349e powerquicc ii pro family device errata freescale pdf fact sheets id and description vendor id format mpc8349fs pa g e 4 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
mpc8349e powerquicc ii pro family fact sheet freescale pdf packaging information id and description vendor id format pbgapres pbga packaging customer tutorial freescale pdf tbgaprespkg tbga packaging customer tutorial freescale pdf product briefs id and description vendor id format mpc8349epb mpc8349e integrated host processor product brief freescale pdf product numbering scheme id and description vendor id format mpc834xefampns mpc834xe family part number scheme freescale pdf reference manuals id and description vendor id format e300corerm e300 powerpc core reference manual freescale pdf mpc8349erm mpc8349e powerquicc ii pr o integrated host proc essor family reference manual freescale pdf mpcfpe32b programming environments manual for 32-bit implemen tations of the powerpc architecture freescale pdf reports or presentations id and description vendor id format pqsecbkgrndrpt backgrounder: the security object ives of powerquicc secure communications processors freescale pdf pa g e 5 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
pqseccryptoperfrpt understanding cryptographic performance freescale pdf users guides id and description vendor id format sec2swug sec 2.0 reference device driver user's guide freescale pdf sec2xswug sec 2.x reference device driver users guide freescale pdf white papers id and description vendor id format nandflashwp how to interface the powerquicc ii pro and powerquicc iii local bus controller to nand flash freescale pdf publickeyperfwp understanding public-key performance freescale pdf return to to p mpc8347e desi g n tools hardware tools analyzers logic id and description vendor id form a tla715/tla721 tla700 logic analyzers the tla700 logic analyzers have th e performance to capture and display the fastest signals and gives you instant insight into the digital and analog behavior of your system so you can quickly find those elusive tektronix - pa g e 6 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
signal integrity problems emulators/probes/wigglers id and description vendor id format cwh - utp - ppcc - hx codewarrior usb tap - jtag/cop interface freescale - guardian - se guardian-se jtag debug tools for powerpc development toolsmiths - probe green hills probe & slingshot high speed on-chipo downloa d and run control. greenhills - wrice wind river ice the wind river ice is a jtag hardware run control device supporting multiple jtag,ejtag,and bdm devices on a single scan chain. it can support connections for up to eight devices simult aneously in a scan chain of up to 128 devices. windriv - models bsdl id and description vendor id form a mpc834x_bsdl mpc834x bsdl models, rev 1.0 and rev 1.1 silicon supports silicon revisons 1.0 and 1.1 (05/23/2005) freescale zip ibis id and description vendor id form a mpc834x_ibis ibis models for 8343e, 8347e, and 8349e supports silicon revisions 1.0 and 1.1.(10/04/2005) freescale zip pa g e 7 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
schematics id and description vendor id format mpc8349sym orcad symbols for mpc8349e tbga device capture library file (.olb) (10/19/2005) freescale zip software board support packages id and description vendor id format integrity/velosity/multi bsp green hills bsp the green hills bsp provi des integrity & velosity rtoses and multi debugger for board- specifi c cross development thr ough the green hills probe, slingshot or p&e wiggler or, if no board is available, to the multi instruction set simulator. greenhills - device drivers id and description vendor id format sec2drivers sec 2.0 device drivers 85xx/83xx sec 2.0 device drivers (03/04/05) freescale zip libraries id and description vendor id format dg06030101 data overwrite detector an installable tool which detects an undesired overwrite. in cludes a white-list of allowable accesses and data filtering. dogav - dg1f030201 exception analyzer an installable tool which dumps critical registers and stack trace-back into a predefined memory area. also, calls an application callback function. dogav - dg1f030301 pa g e 8 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
general buffer pool manager assembler based software that manages buffer pools. supports pools initialization, allocation and release (free). provide s extended protection, such as double buffer release protection (can be disabled) and statistics counters. dogav - operating systems id and description vendor id format cmx00300 cmx tcp/ip tool resell agreement cmx - cmx00300a tcp/ip dhcp client tool resell agreement cmx - cmx00300b tcp/ip dhcp server tool resell agreement cmx - cmx00300c tcp/ip ftp c/s tool resell agreement cmx - cmx00300d tcp/ip imap4 tool resell agreement cmx - cmx00300e tcp/ip nat tool resell agreement cmx - cmx00300f tcp/ip pop3 the cmx tcp/ip pop3 client add-on option provides cmx tcp/ip (see cmx00300, cmx00305, or cmx00310) with f unctionality to support the post office protocol client st andard. a source code example is provided for fast design start up. cmx - cmx00300g tcp/ip ppp tool resell agreement cmx - cmx00300h tool resell agreement cmx - pa g e 9 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
tcp/ip pppoe cmx00300i tcp/ip smtp tool resell agreement cmx - cmx00300j tcp/ip snmp tool resell agreement cmx - cmx00300k tcp/ip telnet tool resell agreement cmx - cmx00300l tcp/ip tftp tool resell agreement cmx - cmx00300m tcp/ip web client tool resell agreement cmx - cmx00300n tcp/ip web server tool resell agreement cmx - cmx00630 cmx-ffs tool resell agreement cmx - cmx00631 cmx-ffs-nand tool resell agreement cmx - cmx00632 cmx-ffs-fat tool resell agreement cmx - cmx00633 cmx-ffs-thin tool resell agreement cmx - integrity integrity integrity is a secure, royalty-free real-time operating system intended for use in embedded systems that require total reliability and fast, deterministic response time. fully integrated with the multi environment and c/c+ greenhills - pa g e 10 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
compilers. velosity velosity the velosity microkernel is small, fast and royalt y free, perfect for cost- sensitive, high-volume embedded projec ts. integrated with multi software tools, it offers a rich set of kernel services, device drivers, bsps and middleware. greenhills - protocol stacks id and description vendor id format moc_ssl_client mocana embedded ssl/tls client mocana ssl/tls client: supports fr eescale chipsets out of the box. small (50kb), fast (2-3x faster than openssl), trusted. supports all major cryptos. royalty free, source code license. free eval: http://www.mocana.com/evaluate.html mocana - software tools compilers id and description vendor id format compiler c/c++ compiler optimizing c, c++, ec++ compilers for freescale powerpc, coldfire, starcore, 68k, mcore and arm- based mac architectures. greenhills - wind river compiler wind river compiler the wind river compiler combines industry leading optimization technology with the flexibility and control needed to fully exploit freescale cpus. windriv - ide (integrated development environment) id and description vendor id format cws - ppc - cmsfl - cx codewarrior development studio, powerp c isa comm processors (solaris) freescale - pa g e 11 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
cws - ppc - cmwfl - cx codewarrior development studio, powerpc isa comm processors (windows) freescale - multi multi multi is a complete integrated de velopment environment for embedded applications for c/c++, embedded c+ + and includes an advanced debugger, profiler, run-time memory checking, pr oject builder, editor, instruction set simulator and more. greenhills - initialization/boot code generation id and description vendor id format mpc8560lbcupmibcg upm tool for powerquicc iii processors (12/11/2003) freescale zip models instruction set simulator id and description vendor id form a e300geniss e300 generic library iss for solaris (09/06/2005) freescale gz e300iss e300 standalone iss for solaris (09/06/2005) freescale gz e300lingeniss e300 generic library iss for linux ppc (09/06/2005) freescale gz e300liniss e300 standalone iss for linux ppc (09/06/2005) freescale gz e300linx86geniss e300 generic library iss for linux x86 (09/06/2005) freescale gz pa g e 12 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
e300linx86iss e300 standalone iss for linux x86 (09/06/2005) freescale gz performance and testing id and description vendor id format kmfgtest 300 kozio's kmfgtest is a stand-alone em bedded software application providing automated system-level test capabilities. it streamlines the testing of computer boards at the end of the production line. kozio - kdiagnostics 100 kdiagnostics is powerful test software providing board-level diagnostics for embedded designs. as an easy to use turn-key solution, kdiagnostics reduces board bring-up times and saves development kozio - return to to p a pp lications home media serve r return to to p orderable parts information order part number package tape and application/ qualification status budgetary price qty p pa g e 13 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
description reel tier 1000+ ($us) t e - kmpc8347evragd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - KMPC8347EZQAGD pbga 620 29*29*1.2p1.0 no commercial, industrial available - - kmpc8347ezuajf tbga 672 35*35*1.5p1.0 no commercial, industrial available - - kmpc8347vragd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - kmpc8347zqagd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - kmpc8347zuajf tbga 672 35*35*1.5p1.0 no commercial, industrial available - - mpc8347evradd pbga 620 29*29*1.2p1.0 no commercial, industrial available - buy from distributor mpc8347evragd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - mpc8347ezqadd pbga 620 29*29*1.2p1.0 no commercial, industrial available - buy from distributor mpc8347ezqagd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - mpc8347ezualf tbga 672 35*35*1.5p1.0 no commercial, industrial introduction pending - - mpc8347vradd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - mpc8347vragd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - mpc8347zqadd pbga 620 29*29*1.2p1.0 no commercial, industrial available - pa g e 14 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm
- mpc8347zqagd pbga 620 29*29*1.2p1.0 no commercial, industrial available - - mpc8347zuajf tbga 672 35*35*1.5p1.0 no commercial, industrial available - note: z not all orderable parts are offered through our online samp ling program. for further assist ance in selecting a simil a request for a sample order advice. z refer to samples faq for more information. z looking for an obsolete part? check our new part number search return to to p related links link freescale's advanced telecommunicat ions computing architecture (atca) link industrial control link n etworking link powerquicc communications processors link security processors return to to p http://www.freescale.com/ | site map | terms of use | privacy practices | what is this? | ? freescale semiconductor, inc. 2004 - 2005. all rights reserved pa g e 15 of 15 mpc8347e product summar y pa g e 30-nov-2005 file://g:\mpc8347e%20product%20summar y %20pa g e.htm

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